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Advanced PCB Layout Course questions

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  • Advanced PCB Layout Course questions

    Hi Robert. I'm following the Advanced PCB Layout Course.
    I have 4 questions on lesson 3 and 1 on lesson 4.

    Lesson 3:
    1. Dielectric constant of PCB materials depends on frequency. But what frequency should we consider? For example, I have a track: a clock at 1 GHz. Should I consider this frequency?
    2. Correct me on the following if wrong: in the lesson, you talk about crosstalk and a method to reduce it is to trace tracks with distance referred to H, where H is the distance between track and reference plane. Now a question: I have read the 3W rule, where W is the width of the track. What rule should I follow?
    3. You suggest that a power plane can be used as reference for controlled impedance tracks. If the power plane is fragmented?
    4. Is it necessary that a reference plane should be solid on a entire layer? Or only in the area where we have controlled impedance tracks?
    Lesson 4:
    1. At the end of the lesson you show several stackups. Consider the following 12 layer:
    1 Signal
    2 GND
    3 Signal
    4 Signal
    5 Power
    6 Power
    7 Power
    8 Power
    9 Signal
    10 Signal
    11 GND
    12 Signal

    If we have controlled impedance on layer 3 and layer 4 (similar on layer 9 and layer 10), what are reference planes?

    Thanks for the reply.

    Best regards,

  • #2
    Hi Tom,

    3.1 I usually look at parameters at 1-5GHz (PCIE). PS: I have seen many PCBs build from standard materials and up to 3.5GHz working oki.
    3.2 I work with the H rule. Often I just route tracks as far as I can from each other - in many high density PCBs this means, tracks are still routed quite close to Each other. 3W is very luxury and in many high density boards it is not possible .. that is why I work with H.
    3.3 If power plane is fragmented, no that may not be a good reference plane.
    3.4 it needs to be solid at least above/below the tracks you would like to reference to that plane + you may want to consider return currents through GND / Power / neighbor pins of the chips connected together and have the reference plane also in that areas.

    4.1 Reference planes would be 2 and 5 (if they are both solid)