Advanced PCB Layout Activities question

[ZsoltFulop]

Hi
I am little bit confused with the activities in Advanced PCB Layout course,
Do I have to do my own project and route everything,or I always have to load the downloaded activities and work with it?
I done my own project,and tried to follow the activities without the uploaded files and just realized now,there is some download files with the Lessons.

[chitransh92]

ZsoltFulop ,
The download files are for reference...
If you do a fresh PCB project and do every thing on your own it will enhance your skills and you will understand all the pitfalls that you will not understand other wise..

robertferanec can suggest better.. He is the one who developed the course..

Thank you.

[robertferanec]

ZsoltFulop if you can practice the activities on your own project, you can do that (just upload the screenshots where you did that specific activity on your own board). If your project doesn't have some of the things we are talking about in the course (e.g. memory interface), you can download the course activity files so you can practice memory layout or length matching activities.

[ZsoltFulop]

Thanks for the answers.
It was a bit confuse me as it saying "for this week activities you have to work on ... files" .
So if I understood well I have to work on my own board and if I would like to practice or copy some ideas how to route I need to check the dowload files.
That make more sence to me

[ZsoltFulop]

I have got one more thing which is not clear for me:
is it only voluntary activity to do the baseboard?
So when I will finish the course and need to send the project files, is it enough to send only the module board project?

[robertferanec]

It is important to work at least on 1 activity per lessons. If you can find a Module activity for each lesson, than it is fine, you do not need to work on baseboard (but some activities are interesting also on baseboard).

PS: Please, do not upload the project. Only upload screenshots - that is much faster and easier for me to check. Thank you.

[ZsoltFulop]

Thank you I will do.
I have got one more question which is about the VIA.
On the course you did talk about we have to make sure about the via size which will carry the Power (so it might can carry big currents) and these VIAs normally through hole VIAs.
I am just wondering what would happen if for example I will use the same size VIA(size:0,4mm,hole:0.2) for a Power net but it will not go through on every(12 Layer) only go from the 1st Layer(TOP) to the 5th or 6thor 7th Power Layer? so it will not causing any problems in the 10th layer where is the signals and on the 12th layer where is the bottom side parts?

[robertferanec]

I am just wondering what would happen if for example I will use the same size VIA(size:0,4mm,hole:0.2) for a Power net but it will not go through on every(12 Layer)

I have not done that much (only a couple of times), but it looks like it may be a common technique to use uVIAs or blind VIAs for power delivery (some people already mentioned to me, that they do it).

[Vinod Devrari]

Hi Robert,
I am facing a problem in length matching, It is displaying an error "this primitive is not coupled within the max range; 10mil ofDiff pair Routing rule"

How to resolve this problem. Also, it is showing some values "<15mil". I am not able to resolve this issue.

Currently, I am using AD 20.0.1

[ZsoltFulop]

In my knowledge This is looks like an impedance rule what you did set up earlier. You might have to change the track width to get the impedance what you need.
But I am not professional, I don`t want to confuse you, wait till Robert answer for this.

[robertferanec]

These are not length matching issues. This is just telling you which segments of track are out of tolerance comparing to what is set in the rules for differential pair routing. For example, if your rules says, that space between tracks in your diff pair should be 10 mils, when you route them with space 12mils, then you will see this message.

Try to play with "uncoupled" length in the rules, this may help: https://designhelp.fedevel.com/forum...ferential-pair

[Vinod Devrari]

Hi Everyone,
This problem is solved. In that case, I have mistakenly added an extra rule for Diff pair routing. When I have deleted that rule there is no more error marker.

Thanks for your support.