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Parallel termination resistor placement (For DDR ACC signals in my case)

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  • Parallel termination resistor placement (For DDR ACC signals in my case)

    Hi everyone,

    I am concerned with my routing of parallel termination, they should be as close as possible to the receiver and after them in general, I wonder if what I could be doing here is harmful or not:
    Click image for larger version

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    As you can see, I dig up with through all vias (in blue) from internal layer to top layer(to reach my DRAM pins) rather far away from the pins, it gave me space for length tuning. If I use these through all vias to route direclty to my terminationn resistors, I am afraid of them being too far, and signal reaching them before reaching the DRAM pin.

    However, I according to this article ( ), Lee Ritchey said: “In my classes I say ‘You can put the terminator a kilometer away if it makes it easier for you and people look at me like I am crazy. It’s hard to get people to think about fields and waves because they get so wrapped up in currents. When you understand that you have sent an electromagnetic field past that pin, which was the goal, it’s pretty straight forward.” “

    Should I still use these vias as path to my termination resistors ?

    Thank you in advance!

  • #2
    where are the termination resistors? to keep stubs small, ideally you would like to have the memory pins on the way to the termination resistors.