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groups the signals in ddr3 using fly-by in schematic and pcb

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  • groups the signals in ddr3 using fly-by in schematic and pcb

    Hi,
    What is the command to groups the signals in ddr3 using fly-by in schematic and pcb (address,command,control signals in single group)

  • #2
    You can use a blanket directive to cover the particular nets and assign a net to the blanket using a net class parameter set directive.

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    • #3
      please explain step by step process to be followed

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      • #4
        TRY AND GOT IT THANKS, HOW TO ASSIGN ONE BLANKET NET NAME MORE ONCE IN SINGLE SHEET

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        • #5
          If I used more than one like

          "Net Class ClassName:A1" & "Net Class ClassName:A2" in single Altium schematic sheet I found below error


          [Error] Compiler Duplicate Net Names Wire N000-1 (Inferred)

          kindly support to solve the problem........



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          • #6
            tripple check if you have no duplicate netname lkike it implies. if you double click the schematic class entry i think you can enter more than 1 field.. both need to be different. (can't check on my phone right now) but i hope you can find it your self.. also google is sometimes very helpfull

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            • #7
              shereesubahan, if you still need, you can have a look how we create net classes in our open source projects here (you can download the full altium files): https://www.imx6rex.com/ The OpenRex is using Fly-by: https://www.imx6rex.com/open-rex/

              Click image for larger version

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              • #8
                What type of Via can be used for connecting two DDR3 device & what is the Via size, what can be the trace width & clearance

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                • #9
                  that is fully dependend on the chip you choose, the speed your running,, the layerstack and technology capabilites of your supplier..

                  normally I would say when using 1mm pitch BGA go with 18/8mil via's tune them to be 50 Ohm (use saturn pcb toolkit)
                  trace witdh/spacing has to be calculated to your layerstack... if you are using 40 Ohm for DQ )(dpends on your ODT) and 50 Ohm for Address/Command lines. and 100 Ohm for DQS/CLK signals.
                  ideally spacing between DQ signals are at least 2x trace witdh more is better. 3x tracewidth between DQS/CLK and other signals.

                  you can use through hole via's for this up to 533Mhz DDR baseclock if you go higher then i would prefer blind / buried via's to minimize stub length

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                  • #10
                    shereesubahan, depends on several factors, e.g. placement (e.g. if you have two memories on different data bus on top of each other, if you have two memories on top of each other using same data bus, if you have all the memory chips on the same side of PCB, ....), target PCB price (are you going for cheap PCB or you can use something more expensive), etc. If you like, you can download Altium files of our iMX6 Rex projects. The iMX6 Rex Module is using uVIAs, OpenRex is using through hole VIAs only. You can have a look how it is done - there are also stackups and you can re-use the same trace width and clearance.

                    Here are links to the projects:
                    - iMX6 Rex Module https://www.imx6rex.com/
                    - OpenRex https://www.imx6rex.com/open-rex/

                    Hope this helps.

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