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VIAs under THERMAL PAD DRC

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  • VIAs under THERMAL PAD DRC

    Hello guys,

    The PCB fabrication plant, wants me to maintain 0.2mm clearance between VIAS and PADS of same net and any net. Hence I created rules like in the following picture :

    Click image for larger version

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    Click image for larger version

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    The problem what I am facing is, Altium throws error for the VIAS under the thermad pad of QFN. I couldn't find out how to solve this problem, could anyone help me out please !

    Thanks in advance.

    Regards,
    Naveen
    Attached Files

  • #2
    If you scroll down, in one of the other categories you have a special Via Under SMD rule.

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    • #3
      Hello Mairomaster,

      I tried enabling VIAS under SMD PAD, but still the Altium shows DRC error : Clearance contraint.

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      • #4
        Add an exception for the particular footprint.

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