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VIAs under THERMAL PAD DRC

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  • mairomaster
    replied
    Add an exception for the particular footprint.

    Leave a comment:


  • Naveen-Krishnan
    replied
    Hello Mairomaster,

    I tried enabling VIAS under SMD PAD, but still the Altium shows DRC error : Clearance contraint.

    Leave a comment:


  • mairomaster
    replied
    If you scroll down, in one of the other categories you have a special Via Under SMD rule.

    Leave a comment:


  • Naveen-Krishnan
    started a topic VIAs under THERMAL PAD DRC

    VIAs under THERMAL PAD DRC

    Hello guys,

    The PCB fabrication plant, wants me to maintain 0.2mm clearance between VIAS and PADS of same net and any net. Hence I created rules like in the following picture :

    Click image for larger version

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    Click image for larger version

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    The problem what I am facing is, Altium throws error for the VIAS under the thermad pad of QFN. I couldn't find out how to solve this problem, could anyone help me out please !

    Thanks in advance.

    Regards,
    Naveen
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