Differential pair via to via clearance

[Mihai]

Hi,

Is there a rule or standard on how much should be the clearance between the vias of a differential pair which is passing from top to the bottom layer? e.g. is correct to have the vias as the way are in the attached image? Or I have to define a specific clearance rule just for this problem?

Cheers,
Mihai

[Lakshmi]

That should be okay.

[Mihai]

thanks Lakshmi.
Also I have a question and maybe robertferanec can answer to it or others. How do you set the rule for differential pairs to be length matched on each layer they travel? On Altium 18, I see that is given the whole length on all layers, how can I imply a separation and to ensure length matching on every layer?

Cheers,
Mihai

[Lakshmi]

From the Manufacturing team you'll get the 90 Ohm impedance trace width and separation and add that.
idk how do you do this in Altium (I haven't used yet) since i work in KiCAD.

[Mihai]

Hi Lakshmi I am not referring on how to route the differential pairs with a given impedance, I am referring on how to keep the same length of the pair on each layer where is routed. Especially if there a rule for that, other than just measuring the selected object on a given layer.

Cheers,
Mihai

[robertferanec]

How do you set the rule for differential pairs to be length matched on each layer they travel?

We do this in Altium manually. I am not sure if there is a straight forward rule to check this.

About the VIA space - I normally use the same clearance as is set for the differential pair.