Polygon strategy

[alican.ozpay]

Hello everyone,

I'm following different way for polygon strategy according to my projects but ı have a few questions.

1-) Is there any strategy for polygon. Like advantage or dis advantage?

2-)is polygon strategy way of attached Picture true ? Is there any advantage of disadvantage ?

*Note: Under my PCB is gnd polygon completely.

[barismetin]

Hi, Dear Alican the purpose of the polygon is create the shortest and easy connection between power planes usually. In order to eliminate the trace capacitance and inductance polygons are the best way to do it.I highly recommend making one solid ground polygon thought the board if possible. How many layer is your design?

[alican.ozpay]

Hi,
Thank you for reply.
My pcb has four layer and my bottom layer is completely gnd polygon.
Top layer has two polygon. Half side is battery polygon other half side is gnd. My second and third layer is same top layer polygons.
My question is, is there any disadvantage divided polygon like at top layer?

[barismetin]

No, I do not think there is a disadvantage in that case. How many voltage levels you use also I recommend you use via stitching to connecting all GND together

[robertferanec]

There are some things what you would like to think about, for example:
- you may want to have one big polygon under the whole PCB (if all components are using the same GND)
- you may want to have power and gnd planes on neighbor layers placed close together as it creates "capacitor" and it may be in some cases useful
- you may want to have bigger gap between planes (it is easier to manufacture and it helps minimize noise crossing between the planes)
- for high currents you may want to place same polygon on several layers and connect them through many VIAs
- etc.

[alican.ozpay]

Thank you Robert for your answer.

I'm a new hardware design engineer. I do not know so much about polygon pour. I want to learn.

As ı understand, there is no problem my polygons but ı'm wondering polygon pours strategies still. I want to dominate about polygon pours.

Like you said, if a power and gnd planes on neighbor layers placed closed together they will effect like capacitor. Which cases it is useful ? Which cases it is not useful ?

What is the bigger gap between planes? For examples, How much gap should ı space out between planes ?

barismetin

Mr.Baris metin

There is three different voltage levels on my pcb but there is one voltage level on my planes. This is battery level. Thank you answer.

[robertferanec]

Like you said, if a power and gnd planes on neighbor layers placed closed together they will effect like capacitor. Which cases it is useful ?

- for the kind of boards I design (digital boards) it is almost always wanted scenario (helps with power delivery and filtering / noise reduction)

What is the bigger gap between planes? For examples, How much gap should ı space out between planes ?

- depends how small or packed your layout is. Generally I try do not go below 0.2mm clearance between planes, but rather minimum is 0.3 - 0.5 mm clearance between planes