SDRAM INTERFACE WITH FPGA

[shereesubahan]

HI,
NEED DEVELOP A PCB TO INTERFACE WITH FPGA AND SDRAM (IS42S16160J-6TLI), SO KINDLY SHARE WHAT ARE THE POINT TO BE CONSIDER IN DESIGN (LIKE TRACE LENGTHS,COMPONENT PLACEMENT ETC....,)

[Paul van Avesaath]

there are a lot of discussions in this forum that cover these things, try and look back in the listings.. i find the micron layout guide pretty good..

[robertferanec]

This is slow memory (looks like clock frequency 166MHz: http://www.issi.com/WW/pdf/42-45S83200J-16160J.pdf ). You should not have problems with this. There should not be very strict length matching (most people would not even length match it - I have not length matched some SDRAM interfaces, no problems), but if you are not sure and you want to do some length matching, then make add/cmd/ctl tracks similar length, all data tracks similar length (shortest) and clock the longest.

Usually the biggest problem for these connections is not length matching, but possible crosstalk (e.g. if board is not carefully designed on 2 layer PCB) or if you have more devices connected on the same bus, then reflections may be problems.

[shereesubahan]

Hi,
In SDRAM based PCB design , DATA lines & clock line are routed in one layer & all other signals (Address,CKE,DQM,DQL etc...,) are routed in another layer.

Total PCB stackup is as follows

1) Top
2) GND
3) Mid layer1 (signal) -----> [SDRAM DATA lines & clock line]
4) GND
5) POWER
6) Mid layer2 (signal) -----> [all other SDRAM signals]
7) GND
8) TOP

Kindly suggest any modification needed in layer stackup & SDRAM signals routing.

[robertferanec]

This stackup seems to be ok.