Hell all,
I would like to ask 2 questions about a specific design in attachment. The Altium project is from TI, reagarding a 4L BMS board.
1) On the left side of the board where the Hercules MCU is located that logic area has separated GND Polygon Planes (PGND, CANGND, etc). Is it better than using one single plane for all signals and power areas? What is the benefit?
2) In this design all layers are Sig + Vcc and free area is GND for all layers. Also the signal tracks from BQ79606 to the connector path are not reneferenced to any GND layer. According to Rick Hartley's presentation, one of the best (lower impedance) stack up is GND for Bottom and Top and in the middle layers (2+3) Sig+Vcc. In such a design case (BMS) which is the best option considering battery measurements accuracy and EMC performance?
I would appreciate your feedback.
Thanks,
George
I would like to ask 2 questions about a specific design in attachment. The Altium project is from TI, reagarding a 4L BMS board.
1) On the left side of the board where the Hercules MCU is located that logic area has separated GND Polygon Planes (PGND, CANGND, etc). Is it better than using one single plane for all signals and power areas? What is the benefit?
2) In this design all layers are Sig + Vcc and free area is GND for all layers. Also the signal tracks from BQ79606 to the connector path are not reneferenced to any GND layer. According to Rick Hartley's presentation, one of the best (lower impedance) stack up is GND for Bottom and Top and in the middle layers (2+3) Sig+Vcc. In such a design case (BMS) which is the best option considering battery measurements accuracy and EMC performance?
I would appreciate your feedback.
Thanks,
George
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