Is this correct? Is it good?

[M. Namvar]

thank you very much

[robertferanec]

can I connect the power pins to a power plane with uVia?

- occasionally I do that (if there is no other way), but through hole via connection is better for powers.See my answer below ..

I mean why do you use through-hole via and go to the bottom layer?

- through hole via provides better connection (lower inductance, higher currents possible, ....) comparing to the uVIAs which I use.

[robertferanec]

What is the effect of multiple pads per single via (like this BGA and with multiple capacitors).

- it is a lot about inductance

I would recommend you to watch my Decoupling capacitor youtube video series to understand how important it is to keep connections of capacitors short:
https://www.youtube.com/playlist?lis...uvkR_TjpnF1Z7f

Very simply to say, if you have a capacitor which is connected by a long track, it is not going to do good. Therefore you would like to have as short connections from pads to vias as possible.

I know this doesn't answer you question directly, but, there is no really reason to simulate it as I would not recommend to use it for the reasons above.

[M. Namvar]

thank you
another question: can I connect the power pins to a power plane with uVia? I mean why do you use through-hole via and go to the bottom layer?

[qdrives]

robertferanec do you still have access to that simulation tool from Keysight?
What is the effect of multiple pads per single via (like this BGA and with multiple capacitors).
Or a structure like in the picture below...

[robertferanec]

For power pins (including GND) I always try to have 1 through hole via per pin. Only if not possible (e.g. no space on bottom for components), only then I can connect more than 1 power pin to 1 via. So, personally, I would not route it that way.

[M. Namvar]

hi

Is this routing appropriate?