Design rule - Via stiching

[k.ifantidis]

Thank you very much chitransh92. I'm going to try the keep out solution to see how this work-out. I hope it doesn't keep out the polygon pours.

[chitransh92]

Hi k.ifantidis ,
Altium checks the rules within the routing layers and Does not detect rules for the Mechanical and other layers.
Even if you select the text on overlays and vias and create a rule it will not flag up the error.

You can follow below tricks.
- Place a Keep out underneath the logo and there will be no via stiching in that area.
- (A laborious approach) You can start with and extra layer as "temp" as signal layer and copy all the primitives from top overlay to this signal layer and then the tool will flag the error when you run design check. Just do not select it for gerber outputs...


Do let us know if you find any better solution.

Thank you.

[WhoKnewKnows]

I'm not sure you can write a rule that will prevent stitching vias from being placed like you don't want, but perhaps there is a way to programmatically identify vias that are placed where you don't want, and then delete them all at once?

It seems like a good way to go would be to write/develop a design rule that detects the occurrence, then after stitching has been done, run the rule check and manually select and delete the vias that are marked by the rule as DRC errors. Observe whether the rule has found all of the vias you don't want. Also make sure the rule hasn't identified vias for deletion that should remain.

Once you're confident that the rule is correctly identifying vias you want deleted, on future designs, you can now apply the rule's query language directly to the PCB filter panel and have the PCB filter panel automatically select all of the vias you don't want, which lets you delete them all at once.

[k.ifantidis]

If a via is tented, then it has soldermask over it, and overlay objects can cover the via no problem.

Yes this is correct but some of the manufacturers does not apply full-tending and I have to be careful in order not to corrupt a brand name or model with via stitching.

What's the purpose of creating such a rule?

I need this rule in order to prevent via stitching be generated on top of top or bottom overlay layer. Just as there is a rule for via stitching to keep distance from tracks, arcs and some other objects i'm looking for a rule that would do the same for top and bottom overlay layer.

Thank you for your answers robert and whoknewknows. It is not big deal to delete vias manually after being created with stitching but I'm always looking for ways to improve staff and tools that I use. If I find how to do this after communicating with Altium support I'll let you know !


Regards, Kostas.

[WhoKnewKnows]

Typically, PCB manufacturers will automatically void objects on the overlay layers where there are voids in the solder mask layer. That is, overlay is usually only printed where there is soldermask to print on. If a via is tented, then it has soldermask over it, and overlay objects can cover the via no problem. What's the purpose of creating such a rule? I think it can be done, but I wouldn't enable it for online checking.

[robertferanec]

I am not aware if something like that exists.

[k.ifantidis]

Hello there !!

I'm trying for at least 1-2 years now to figure out how to add a rule that will prevent via stitching to be placed on top-overlay/ bottom-overlay layers. Is there anyone that can help me with this ? It has become annoying deleting vias manually.

Thank you in advance.