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  • VIA in the PAD?

    robertferanec
    Administrator
    robertferanec , thanks to your youtube video about VIA in the PAD, I agree that it will give good routing options, but just got a concern addressed by our assembly house. According to him, by placing a via in the PAD actually, there is a big hole that will absorb the solder and so solderability and reliability issues may arise. I am wondering do you agree with this comment? Do we need to ask PCB manufacturer to fill these VIAs during surface finishing? Or any other suggestion?

  • #2
    Via-in-pad construction typically requires that the vias will either be plated shut, or filled with an epoxy and plated over, then pad surface finish (ENIG, etc.) is applied. There are few times where it's possible to have via in pad and not be concerned with starving the solder joint of solder. But, if doing an entire design as via in pad, you may as well allow all vias to be filled and plated over. Selective via filling will cost more. + Filled and plated over vias looks pretty sleek TBH. Don't forget to turn on tenting

    EDIT: Sorry, I just realized you asked Robert. Looking forward to Robert's answer. Perhaps I missed something. Speaking of missing something, I'm surprised your assembly shop and or fab shop didn't recommend filling and plating over vias instead of simply suggesting to avoid via in pad designs.
    WhoKnewKnows
    Senior Member
    Last edited by WhoKnewKnows; 05-29-2021, 04:46 PM.

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    • #3
      WhoKnewKnows
      Senior Member
      WhoKnewKnows , Thank you very much for your valuable comment, me too, looking forward to Robert's comments as well.

      Actually, my assembly house was correct indeed, I should ask PCB manufacture to treat VIAs differently, correct?

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      • #4
        Via in pad on chip components and ICs with small terminals will typically starve the solder joint of solder.

        On larger pads, like the thermal pad at the center of a quad IC, you can get away with having a few vias that aren't filled and plated over, but you have to coordinate the shape of the solder stencil openings over that same pad. The theory is that on large pads it's good to somewhat limit total solder anyway, so some can be wasted by the via being there. The stencil openings should apply solder to the large pad area where there are no vias so that solder paste isn't dispensed directly into the vias during application. This would be for a design that isn't via in pad everywhere and you just want some better thermal performance. On the design that's entirely via in pad, it's better to fill and plate over all vias.

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        • #5
          A few recommendations if you don't use VIA filling:
          1. if you have big PAD and more VIAs are used (e.g. QFN thermal PAD) is its better to place VIAs symetrical onto the PAD. It is help to avoid wrong automatic IC positions (aligns) under reflow process.
          2. Take attention to do not place VIAs on paste mask as WhoKnewKnows said above.

          Attila
          VUHA
          Junior Member
          Last edited by VUHA; 05-30-2021, 10:48 AM.

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          • #6
            The assembly house probably knows that filling or capping a via is expensive. I was working on a design and it would almost double the cost of the board (€21 -> €38).
            It can help reduce the inductance. If it is not needed, do not do it.

            On the remarks that you do not need to fill for bigger pads: the hole size is important. Say small than 0.2mm is ok, but this would be better answered by the assembly house.

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            • #7
              I do not really have much to add, the question was answered correctly. Also, I do not use VIAs in pad, so I would not be the best person to answer (even after creating the video, in the final PCB we decided not to use VIAs in pad as it was not necessary and it would just increase it's price).

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