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Question About Placement Decoupling Capacitor for DDR3 Memory

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  • Question About Placement Decoupling Capacitor for DDR3 Memory

    Hi Robert Feranec.
    I have a question about placement decoupling capacitor for DDR3 memory.
    Where is the best place to put decoupling capacitors for memory?
    Behind the memory or next to the memory?
    Micron's document recommended to be next to the memory.
    But some say it should be behind the memory.
    Which is more principled?

  • #2
    It mainly depends on where your power plane layer is and also have a look at the Evaluation board and see how they have done.

    For more details, please watch the below video @47:11.
    PCEA Grand Opening Event- Presented by Rick HartleyThe Printed Circuit Engineering Association (PCEA) is an international network of engineers, designers, fa...


    • #3
      robertferanec also has a recent video where he showed that under the right conditions, the proximity of the decoupling caps matters less.

      Also worth considering meeting the DDR manufacturer recommendation(s) in case a problem comes and you request their help troubleshooting.


      • #4
        It depends also on design. For example, if there are two chips in the same place (one on the TOP and other on the BOTTOM), the only way is to place decoupling capacitors around the chips. If all the memory chips are for example only on the top, you may place capacitors on the bottom, however it may be then difficult to route the memory chips (especially if you are using through hole VIAs only).

        But the simple answer is, often decoupling capacitors for memory chips are placed around the the chips.


        • #5
          Dear Lakshmi,WhoKnewKnows,robertferanec Thanks
          Thank you for your answers


          • #6
            Just one more question
            Some people say that the Chinese manufacturer is not of good quality, so the capacitors should be left behind in DDR3.


            • #7
              Manufacturer of what?

              PS: I am not sure what you mean, can you provide a link where people say it?


              • #8
                In the DDR length matching issue and especially considering DDR3 and DDR4 timing, we have to consider the traces which are inside the DDR controller package and also the trace length that sits inside the DDR chip. Usually manufacturer, either controller or DDR chip, publish this info and it is available, Then the DDR trace length will be the sum of three sections, DDR controller + PCB + DDR chip, correct? So wondering how AD handles the case? Can we import package trace data to AD?


                • #9
                  JohnsonMiller you might want to start a new post about length matching considerations, since this post is about capacitor placement. However, I think if Altium doesn't handle this natively, you should likely be able to cook something up using a custom Xsignals setup.