Controlled impedance - Lenght matching.

[zd2020]

Hello all,
My project has got STM32F429ZIT6 microcontroller, IS42S16400J SDRAM and 3,5" TFT. I didn't make impedance controlled multi-layer PCB before. I'm working on it to learn the details of this issue. I learned many things from Dear Robert's contents. Thank's to him once more again.
I have got following questions. I'm very glad if anyone can guide me.

1. I didn't find a design guide about SDRAM. So i couldn't reach any information about impedance matching requirements of the chip. But when i google it, i found this web site: https://pcbartists.com/design/embedd...am-pcb-layout/ It says the following info.
   • A square wave frequency of 200 MHz contains significant high frequency components as high as 1 GHz. All high speed routing layout rules need to be followed. No hard bends, no stubs on traces and no broken ground plane under any trace. MY QUESTION: Maksimum microcontroller frequency is 180MHz and minimum rise time is 2,5ns. How the releationship are there between the risetime and 1Ghz frequecny component?
   • The trace impedance matters. Datasheet of IS42S16400J, an SDRAM chip compatible with STM32, uses 50 ohms load for deriving its IO characteristics. Trying to achieve roughly 50 ohms characteristic impedance on all traces is a good idea to prevent reflection of signals. While this is not absolutely important, it is important to use the same trace width for all traces to maintain uniform line impedance across all SDRAM signal lines. MY QUESTION : He says that it is not absolutely important and lenght matching is enough. I don’t understand why are they wrote like that? I didn’t find any information about Input / Output impedance of SDRAM except a schematic at page 17 at section AC Test conditions section. But i couldn’t comment it on how should i understand characteristic impedance should i set from the datasheet.
   • All signal lines must be referenced to the clock line for length matching as all signals are valid at the rising edge of the clock. All signal lines should be matched to within +/- 400 mils of the clock trace. If multiple clock signals are routed, they must be matched to within +/- 20 mil of each other to prevent clock skew. MY QUESTION: How are they understand the +/- 400mils tolereance
   • Consult the AC timing section of the SDRAM datasheet to find out the maximum allowable skew across signal lines. 0.15mm of unmatched length causes ~1ps of skew. 50ps of skew is acceptable in most STM32 SDRAM PCB layouts, but lower the skew – the better it is. MY QUESTION: I don’t understand where are they undersand it from the datasheet.
   • Try not to push your luck to the boundary with inconsistent layout and length matching. While it might work most of the time, you may have data corruption as temperature swings around the system because propagation time and skew change based on temperature. MY QUESTION: Are they sure? 😊
2. Should i think all the address/data lines and control lines like CS, WE, CLK, BA0/1 and etc as a 50ohm single ended line? Am i make all of them to lenght matching? What is the tolerance of the lenght matching? I'm asking it because it is not quite easy to do it with 4 layer board.
3. How should i make the connections between the microcontroller and the TFT? Should i think them as a 50 ohm single ended line?
4. I have spoken with 3 different PCB manufacturers. I expected that they has got a standart stack up. I should get them and enter it to the Altium. And then i will draw the PCB at required/calculated trace width/space. But all of them requested the design from us at the begining and then told me that they will calculate/check the design. But if they couldn’t manufacture it, i should redraw it completely. That’s why the logical way is to get at least the standart stack up at first. Am i wrong? Why the fabricators do it like that?
5. One Fabricator write “copper 0,0175mm and plating to 0,035mm.” Which value shoud i write to the Altium stack-up settings?
6. My 4 layer stack up is Signal Layer 1 / Ground Plane / Power Plane / Signal Layer 2. The referance layer of Signal Layer 1 is Ground Plane. It is ok. But referans plane of the Signal layer 2 is too far away from the Ground Plane. Can i imagine that the power plane is a referance plane of the signal layer 2?

It is quite long. I apologize.
Thanks in advance for the answers.
ZD

[qdrives]

1) Going through your points.

A square wave is made from multiple sinusoidal waves. Often in 1, 3, 5, etc. times the base frequency. Now as you mention, the rise time is 2.5ns, so it is not really a square, but a trapezium. It still requires multiple frequencies to make. There are many video's on EMC and signal integrity that shows details. Take for instance this one: https://www.youtube.com/watch?v=qVREULDBtjk
More video's are from Eric Bogatin.

Trace impedance is depending on the dielectric, trace width and distance from planes (microstrip / stripline). So the width may not always be the same to get a 50 ohm impedance. Length matching may not be required much as it mainly depends on the timeframe. From memory, a 100MHz signal can have 50mm length difference without much problems. It was in a video from Rick Hartley,
90 degrees bends are only starting to get problematic above 20Gb/s

400mils = 10mm, signal traveling at about 150mm/ns. So if you need the signals to arrive within 1ns, you have 150mm length matching tolerance. NOT 10mm! Do note that you already mentioned that the rise time is 2.5ns, so 1ns is less then half of the rise time.

It takes to for the signal to travel from the MCU to SDRAM. As mentioned, the signal travel about 150mm/ns (or 0.15mm/ps). With difference in length, the signals arrive at a different time. The time is more important than the length. The maximum time difference (AC timing) will be in datasheets. Often a trick to use is to make the clock line the longest.

Temperature may be a factor, but as mentioned, I do expect you to have plenty of room for tolerance.

2) See my remarks above on length tolerance.

3) TFT displays are terrible in details. And TERRIBLE in EMC. I once asked Istvan Novak about the Z0 of FPC, but he could not answer. From what I could find it is closer to 70 ohm. Make a good EMC Gnd connection between your board and the LCD display! You may need to a add series termination too.

4) Most fabricators have a standard 4 layer stackup, but they are terribly bad for SI and EMC. See video's of Rick Hartley where he shows better stack-ups (including 4 layer).

5) Yep, that is a good question. I would say it depends on what you want to do. Do you want Altium to calculate the impedance or do you let the fabricator do it for you?
With the first you would need to put in the final size. The problem with that is that if you are not careful, the fabricator may think you want a base copper of 0.035mm and then add the plating (getting to about 0.06mm).

6) Do you need a power plane? Again, see the video's of Rick Hartley about stack-up.


Better a long question that is clear, then a short one that misses a lot of required details...

[WhoKnewKnows]

You might consider seeing if the MCU manufacturer supplies their part on an evaluation PCB, and buy that PCB so you have a good working model to mess with. These often come with a FPC connector for an LCD and various other peripherals, good RAM memory designed in, etc. See how close the eval design gets you to your target design and modify from there. If you contact the manufacturer, they may supply you with the design files of the eval board so you can start with their design and modify to suit your needs. Regarding signal theory, keep in mind that a signal's "flight time" is governed by both the impedance of the trace and the length of the trace. Often, not only is controlled impedance needed, but matching trace lengths are also needed. A signal arriving in good shape but too late is no better than a too-distorted ringing signal arriving precisely on time. Good luck!