2 RANK 64 Bits 2 Chip DDR3 Routing

[barismetin]

Hi everyone.
I am working on the layout for 2 Rank 64 bits with 8 bits error correction DDR3 PCB layout project. Previously I designed a ddr3 layout with single rank and fly-by topology; hoever, this will be my first time designing something with a 2 Rank system. My first question will be

How should I place the memory chips into the boards? I am thinking of placing one on rank 1 on top and rank2 on to the bottom?
What kind of topology I should use for this project? Fly by T branch? (I only have 1 chip for each rank)
Where should I check to learn more about 2 ranks DDR3 design?

Thanks.

[robertferanec]

just to confirm, by 2 rank you mean everything is shared (data address command control signals), there is just extra chipselect?

for slower memories e.g. up 500MHz you can go away with a lot. For higher speeds it may be more difficult. I would probably go for fly by (that would be safe). It may work also on top of each other, but usually address bus routing would have probably longer stubs so you would need to be sure, these stubs are not going to damage your signal.

[barismetin]

Hi Robert
I really appreciate your help. To answer your first question, yes the data address command control signals shared and chip select is different.

I have two figures about how should layout this PCB. As you can see from image figure 1 one chip placed top layer and the other chip placed to the bottom layer. The DATA and ACC go into the middle and T-Branch to the memory chips. The 2. figure the chips are placed to the top layer and ACC goes fly by and the data goes to the middle and goes T- Branch.

My first question is, do you think figure 1 or figure 2 should be ideal for this project if none can you explain how would you do it please?
My second question is Do you think fly-by for ACC is still possible for figure 1
My last question is how should I connect the DATA signals in this case T branch style?

I appreciate your help and I am very happy with your advanced layout course. Thank you very much!

[robertferanec]

what is the frequency?

[barismetin]

The frequency is 667 MHz.

[robertferanec]

And does reference design use T branch? 667 may be on the edge when it may (not) work. I only routed memories with T-branch up to 500MHz. 800 and above were all fly by with terminations. I do not see termination in your diagram ... so I am not really sure if I would go with T-branch, probably not (unless they used it in reference design and it worked oki - then I would think about it).

[barismetin]

Thank you for your response Robert, I check the Xilinx design guide, and fly by is the suggested topology for my case for ACC signals. One more question, how should I route the data signals two ram memory shares the same data pin. Should I also do fly-by for the data pins or t branch?

[robertferanec]

Several times I routed data signals as T branch - however, that may require data signal swapping as the same data PAD needs to be on the top of each other when the chips are placed in the PCB (e.g. DATA0 pad on the top has to be exactly at the same position as DATA0 pad on the bottom). This way you will keep the stubs as short as possible.

I am not saying it will always work, but this worked for me in many designs. Similar techniques is also used in many DIMM and SODIMM memory modules.