Hi everyone.
I am working on the layout for 2 Rank 64 bits with 8 bits error correction DDR3 PCB layout project. Previously I designed a ddr3 layout with single rank and fly-by topology; hoever, this will be my first time designing something with a 2 Rank system. My first question will be
How should I place the memory chips into the boards? I am thinking of placing one on rank 1 on top and rank2 on to the bottom?
What kind of topology I should use for this project? Fly by T branch? (I only have 1 chip for each rank)
Where should I check to learn more about 2 ranks DDR3 design?
Thanks.
I am working on the layout for 2 Rank 64 bits with 8 bits error correction DDR3 PCB layout project. Previously I designed a ddr3 layout with single rank and fly-by topology; hoever, this will be my first time designing something with a 2 Rank system. My first question will be
How should I place the memory chips into the boards? I am thinking of placing one on rank 1 on top and rank2 on to the bottom?
What kind of topology I should use for this project? Fly by T branch? (I only have 1 chip for each rank)
Where should I check to learn more about 2 ranks DDR3 design?
Thanks.
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