Announcement

Collapse
No announcement yet.

Connect Different Ground

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • Connect Different Ground

    Dear Forum
    In the schematic I have 2 diferent ground net, Analog ground and Digital ground,connected together in 1 point to the 'main' ground as usual . In my PCB i separete the groud with 2 different polygon . Question is : how can I connect them without altium give me a error ?
    If the connection is on top layer, the non problem: I defined a component ,some like a 0 ohm resistor beetwen the gnd planes, so no error from Altium. But, when I want connect in Layer 1 ? No component is possible in L1.

    Thanks for your reply
    Roberto

  • #2
    Altium has net-ties for that purpose. Although connecting it on an inner layer is a bit more tricky.
    However, more important, often splitting ground is not good. From what I understand is that it only makes sense for audio applications (under strict conditions).

    Comment


    • #3
      I think you speak about Net Ties.
      A Net Tie allows to tie two nets with different names, typically analog and digital grounds.
      But as qdrives said, splitting planes is not good.
      It is far much better to get one plane only.
      On this plane, you have a location for analog components and another location for digital components.

      Comment


      • #4
        Separate 2 or more GND is necessary when Example one part have much noise (hight current spike ),and other not. Image a PCB with a FPGA one side and Analog acquisition other side ( A/D + amplifier ecc) . The 2 world coud communicate via digital isolator for example. In this case, 2 GND are necessary.
        Now this 2 GND must be connect in 1 point near the real GND Power supply. So question is like i wrote before.

        Thanks
        Roberto

        Comment


        • #5
          Roibert Splitting planes is not good for EMC compliance

          Comment


          • #6
            Roibert If you create a component with net-tie component property in schlib as well as pcblib, alitum will not show error for shorting two different nets or gnd.

            However, If you want this to do in internal layer, You have to create pads on multi-layer with 0mil/mm hole to acheive this. In this case also, altium shows warnings of multilayer pads with zero drill report you can waive that.

            Comment


            • #7
              Thanks to all to reply, in particular to Mr Lakshamana .

              Yes..It seems the correct solution. In the PCB you can choose any layer you want.

              Thanks

              Comment


              • #8
                Last problem about net tie (top or inner) : last obstacle is that the geometry is fixed ..so the connection point must have the same geometry of the net tie components....of course, tipical of any components .

                There is a way to modify the geometry of a components in --real time-- on the PCB ? The best could be in a Polygon way ..
                I never see it, but maybe a miracle on the 22-02-2022 (:

                Thanks to all again

                Roberto

                Comment


                • #9
                  For qdrivers and Mulfycrowh.

                  Thanks for your reply about the bad choice to split plane. Sayng the true, Im not a fans in spllitting ground plane, because some explain to me that, near the cut, born many problems with impedence. Apart this, in attach I send you a desingn with a very simple requirement ..read analog signal.

                  How you wold positionate the AD and CPU in the PCB ? I will do as show in the design ,and separate with 2 GND plane.
                  Do you think that with no ISO and only 1 GND plane, noise in analog is better ?
                  Maybe can you suggest some tool for proof this (my dream ).
                  Thanks
                  Roberto
                  Click image for larger version

Name:	A1.png
Views:	75
Size:	9.0 KB
ID:	19159

                  Comment


                  • #10
                    How sensitive is the analog input?
                    How much current are you doing in the CPU?
                    I design motor drives. Switching 20A and doing the current measurement (ADC). All with 1 single Gnd plane. My biggest problem is that the Gnd plane also has impedance and will 'lift' the single ended current measurement which needs to be compensated in software.

                    I think you can proof it by doing simulation, but it would be cheaper just to build a proto and measure/test it.
                    The noise on the Gnd plane can also been seen as crosstalk - https://www.youtube.com/watch?v=5EeQPxRdurkband https://www.youtube.com/watch?v=EF7SxgcDfCo
                    Splitting plane: https://www.youtube.com/watch?v=52fxuRGifLU

                    Comment


                    • #11
                      Thanks for reply.
                      I will follow the link and come back if some question.

                      For now, somoone know if my question in post #8 is possible.

                      Thanks again
                      Roberto

                      Comment


                      • #12
                        Well, a net-tie is just like a component.
                        Two pads and a fill or track between them. The shape you make it, is up to you, but that is only the "joint" of the two nets.
                        https://resources.altium.com/p/using...n-requirements
                        I have created a net-tie for an antenna to prevent the Gnd plane to be called Antenna. The width of the pads matched the antenna requirements.
                        Below is another net-tie, the same size as a track to create a Kelvin connection with Gnd. Oh, and this is for analog current measurement (max 70A)
                        Click image for larger version

Name:	Capture net-tie.png
Views:	66
Size:	6.6 KB
ID:	19169

                        Comment


                        • #13
                          Roibert I would also try to do everything with one solid GND plane. The main question is, why the noise under FPGA should spread to the AD area? If properly designed, I believe the "noise" should stay in specific areas and it should not spread through the whole GND plane - if that is happening, then there is something not correctly done (?). But I do not normally design sensitive AD boards, so it would be better to hear a feedback from someone who is designing these kid of boards. Anyone?

                          Comment


                          • #14
                            I never did a measure, but this is my idea:
                            Image we have a square GND plane . We can see it as a infinite resistor in parallel to each other,as I designed in attach
                            file .
                            Image from point P (on the rght) is generated some current . Example, the emitter of a transistor going to GND.
                            The current from P to GND main (the connector) will distribute over all the parallel resistors.
                            Or, in other term, beetwen P and GND Connector will be a Voltage V: any resistor in parallel will see this voltage and
                            will create his current V/R.
                            Of course the Resistor beetwen P and GND Conn will be less than resistor going from P-Analog -Gnd Conn, but not so little

                            Maybe in HF, the inductance of long path will increase resistence and so, flow less current.
                            So, in general, --I think-- the current will be distribuite all over the GND plane ..if we dont cut it.


                            Roberto

                            Click image for larger version

Name:	A2.png
Views:	58
Size:	33.3 KB
ID:	19186

                            Comment


                            • #15
                              robertferanec perhaps some more instructive simulations are called for? What happens when a board is designed as depicted above?

                              Meanwhile, I'm thinking that a high frequency current across the ground plane will happen in conjunction with and in opposite direction of the original high frequency signal and will be closely coupled to the original signal as simulations have shown. A large low frequency current from P to the external ground connector will cause a voltage drop across the ground plane from right to left. If the red line indicates a slot cut, that voltage drop will still cause a voltage drop from one end of the slot to the other. Analog components at the left end of the PCB will experience a ground voltage closest to the voltage of the external ground connector (perhaps that's the reference?). Analog components at the right side of the PCB will experience a higher ground voltage WRT analog components at the left side of the PCB. This is essentially a ground loop effect. Perhaps we'll see some improvement if the red line extends fully to the right edge of the PCB? The red line should probably be widened, otherwise higher frequency ground currents following higher frequency signal paths running parallel to the slot could induce currents in the analog ground plane adjacent to the slot.

                              On solid ground plane theory, high frequency currents tend to closely follow (are coupled to) source signals that cause them. As long as the source signals are routed away from the analog section, the resulting high frequency ground currents should remain closely coupled to the sorce signals and so will avoid the analog parts entirely without need for ground plane segmentation.

                              Comment

                              Working...
                              X