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  • #16
    Roibert your picture doesn't show return currents. Also, you can't really think about resistance, it's important to think about impedance.

    This may help:

    Also, here you can find the full presentation:


    • #17
      For Mr WhoKnewKnows

      Red line in my design means only visual separation beetwen Dig and Analog ; if I have to cut the plane, then I will cut as you said and as i designed some post ago ( in Post #9), that is, a cut start from -right end of PCB-to left a little before main GND.

      For Mr robertferanec
      Thanks for video. I know a little about self inductante and return path ,as you well explained in your videos.(i will look sure soon)
      I have a doubt that this is true only when the current have a frequency hight ,that means, when the inductance have a value comparable with the resistence. When we are in HF (dont ask me please at what frequency..) , then self induction phenomen reduce the 1 way inductor .. and so current is happy to flow back same path because in total the path have less impedance. But at low frequency im not sure anymore ..Example audio, that means we are in the band hundred -20khz max .
      Inductor is not again comparable with resistence at low freq..i think.., so the current will not spread ?
      I will pay for satisfy this curiosity .



      • #18
        I do not know. As I explained, I am not expert for analog sensitive designs, I just said, if I would have to design this board, I would try to focus on one solid GND plane and be sure I understand how the currents will flow there.


        • #19
          Roibert We do not know your application, nor any specifics about it so that makes advice a bit more difficult. As you already alluded to, there is a distinction between high speed and low speed. For high speed, lets say > 10MHz (rise time) the return current flows under the source track. For low frequency < 100kHz, the current take more the path of least resistance. Do note there is a gap in the frequency. That is because there is no hard limit where the one starts and the other stops.

          I asked you about the sensitivity of your analog signal and did not get an answer.
          As I mention I design motor drives. I used a 2 milli ohm resistor to measure the current (up to 35A). The resistance in the Gnd plane, both 'measured' with software and later verified with the PDN analyzer, was about 0.25 milli ohm (estimate about 50mm long and 35um copper thickness). That is 12.5% of the resistor value. Then a op-amp with a gain of 25 was used to get a voltage for the ADC. The measurement error was corrected in software. For the low frequency you are correct that the plane can be seen a set of parallel and series resistors.

          For the layout there are two solutions as depicted below. The top has the circuits correctly grouped / divided / organized. The bottom layout has a split in the layers that would force the current from the digital part to not be able to flow in the analog section in order to get to the connector. Do note that there still is a large section of the (single) Gnd plane connected. Just place a polygon pour cutout. Also note that no traces may cross this split.
          I have used both situations for motor drives and pass EMC tests. My preference (and newer design) is the top one.
          Click image for larger version

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          • #20
            Thanks Mr qdriver for the reply

            and for tell me about the frequency at with plane could be seen as a Resistance or Inductor .

            Excuse if I did not tell you my requirement, because I have not...we was discussing about a general
            question that is : divide or not the plane.

            About your last solution, I not agree ( ..I dont have any measure for say this.. only form a theorical
            point of wiev )

            Let me motivate:

            We agree that GND plane can be seen as a Resistence in serie with a Inductor ,as shown in the attach
            named -Gnd_Plane-.

            R depend on material
            L depend on distance beetwen direct and return path as we know .

            We have that,the total noise on GND is:

            dV = R dI + L dI/dT

            Faster is the rise time, more is the noise dV on the GND plane.

            So,cominng back to your design:

            If the analog part must measure a voltage -VIN- as in Fig1 , then connect the Analog Circuit back
            the Digital ,as you did in both design, I dont like.

            Better solution is in Fig2,where 2 GND plane are in act.
            Note i moved your cut line on the right side of PCB..

            Also Fig3 seems a good solution : Keeping analog near GND-REF, so the L and R are minimized.

            If the Analalog part must measure a voltage refered to DIG Circuit, then FIG4 ..your solution,,,,is OK.

            Are you agree ?

            Attached Files


            • #21
              I would place the analogue power supply close to the analog circuit


              • #22
                Sorry, I should have also drawn a second connector for the analog input.

                Figure 1 is probably missing...

                "... a general question that is : divide or not the plane." - the general answer is very simple: do not split a Gnd plane. However, in this post I do not think that you are talking a general case.

                Is it a differential analog input?
                Single ended but all analog connections are on the same connector and power/digital on another connector?
                Depending on the situation (two connectors), in both my proposals the dI/dt of digital has no influence on the analog part.

                Have you calculated how much the dI/dt could cause? Do note that there is the trace impedance, plane impedance, decoupling capacitors, plane capacitance, etc. That is another reason I asked about the sensitivity you have/need.

                And like robertferanec states, place the power supply for the analog circuit close the circuit.