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  • qdrives
    replied
    Sorry, I should have also drawn a second connector for the analog input.

    Figure 1 is probably missing...

    "... a general question that is : divide or not the plane." - the general answer is very simple: do not split a Gnd plane. However, in this post I do not think that you are talking a general case.

    Is it a differential analog input?
    Single ended but all analog connections are on the same connector and power/digital on another connector?
    Depending on the situation (two connectors), in both my proposals the dI/dt of digital has no influence on the analog part.

    Have you calculated how much the dI/dt could cause? Do note that there is the trace impedance, plane impedance, decoupling capacitors, plane capacitance, etc. That is another reason I asked about the sensitivity you have/need.

    And like robertferanec states, place the power supply for the analog circuit close the circuit.

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  • robertferanec
    replied
    I would place the analogue power supply close to the analog circuit

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  • Roibert
    replied
    Thanks Mr qdriver for the reply

    and for tell me about the frequency at with plane could be seen as a Resistance or Inductor .

    Excuse if I did not tell you my requirement, because I have not...we was discussing about a general
    question that is : divide or not the plane.

    Now:
    About your last solution, I not agree ( ..I dont have any measure for say this.. only form a theorical
    point of wiev )

    Let me motivate:

    We agree that GND plane can be seen as a Resistence in serie with a Inductor ,as shown in the attach
    named -Gnd_Plane-.

    R depend on material
    L depend on distance beetwen direct and return path as we know .

    We have that,the total noise on GND is:

    dV = R dI + L dI/dT

    Faster is the rise time, more is the noise dV on the GND plane.

    ----
    So,cominng back to your design:

    If the analog part must measure a voltage -VIN- as in Fig1 , then connect the Analog Circuit back
    the Digital ,as you did in both design, I dont like.

    Better solution is in Fig2,where 2 GND plane are in act.
    Note i moved your cut line on the right side of PCB..

    Also Fig3 seems a good solution : Keeping analog near GND-REF, so the L and R are minimized.

    If the Analalog part must measure a voltage refered to DIG Circuit, then FIG4 ..your solution,,,,is OK.

    Are you agree ?

    Roberto
    Attached Files

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  • qdrives
    replied
    Roibert We do not know your application, nor any specifics about it so that makes advice a bit more difficult. As you already alluded to, there is a distinction between high speed and low speed. For high speed, lets say > 10MHz (rise time) the return current flows under the source track. For low frequency < 100kHz, the current take more the path of least resistance. Do note there is a gap in the frequency. That is because there is no hard limit where the one starts and the other stops.

    I asked you about the sensitivity of your analog signal and did not get an answer.
    As I mention I design motor drives. I used a 2 milli ohm resistor to measure the current (up to 35A). The resistance in the Gnd plane, both 'measured' with software and later verified with the PDN analyzer, was about 0.25 milli ohm (estimate about 50mm long and 35um copper thickness). That is 12.5% of the resistor value. Then a op-amp with a gain of 25 was used to get a voltage for the ADC. The measurement error was corrected in software. For the low frequency you are correct that the plane can be seen a set of parallel and series resistors.

    For the layout there are two solutions as depicted below. The top has the circuits correctly grouped / divided / organized. The bottom layout has a split in the layers that would force the current from the digital part to not be able to flow in the analog section in order to get to the connector. Do note that there still is a large section of the (single) Gnd plane connected. Just place a polygon pour cutout. Also note that no traces may cross this split.
    I have used both situations for motor drives and pass EMC tests. My preference (and newer design) is the top one.
    Click image for larger version

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  • robertferanec
    replied
    I do not know. As I explained, I am not expert for analog sensitive designs, I just said, if I would have to design this board, I would try to focus on one solid GND plane and be sure I understand how the currents will flow there.

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  • Roibert
    replied
    For Mr WhoKnewKnows

    Red line in my design means only visual separation beetwen Dig and Analog ; if I have to cut the plane, then I will cut as you said and as i designed some post ago ( in Post #9), that is, a cut start from -right end of PCB-to left a little before main GND.

    For Mr robertferanec
    Thanks for video. I know a little about self inductante and return path ,as you well explained in your videos.(i will look sure soon)
    I have a doubt that this is true only when the current have a frequency hight ,that means, when the inductance have a value comparable with the resistence. When we are in HF (dont ask me please at what frequency..) , then self induction phenomen reduce the 1 way inductor .. and so current is happy to flow back same path because in total the path have less impedance. But at low frequency im not sure anymore ..Example audio, that means we are in the band hundred -20khz max .
    Inductor is not again comparable with resistence at low freq..i think.., so the current will not spread ?
    I will pay for satisfy this curiosity .

    Thanks
    Roberto

    Leave a comment:


  • robertferanec
    replied
    Roibert your picture doesn't show return currents. Also, you can't really think about resistance, it's important to think about impedance.

    This may help: https://www.youtube.com/watch?v=H2eQc4DxK30

    Also, here you can find the full presentation: https://www.youtube.com/watch?v=kc9NW2u-vUI&t=0s

    Leave a comment:


  • WhoKnewKnows
    replied
    robertferanec perhaps some more instructive simulations are called for? What happens when a board is designed as depicted above?

    Meanwhile, I'm thinking that a high frequency current across the ground plane will happen in conjunction with and in opposite direction of the original high frequency signal and will be closely coupled to the original signal as simulations have shown. A large low frequency current from P to the external ground connector will cause a voltage drop across the ground plane from right to left. If the red line indicates a slot cut, that voltage drop will still cause a voltage drop from one end of the slot to the other. Analog components at the left end of the PCB will experience a ground voltage closest to the voltage of the external ground connector (perhaps that's the reference?). Analog components at the right side of the PCB will experience a higher ground voltage WRT analog components at the left side of the PCB. This is essentially a ground loop effect. Perhaps we'll see some improvement if the red line extends fully to the right edge of the PCB? The red line should probably be widened, otherwise higher frequency ground currents following higher frequency signal paths running parallel to the slot could induce currents in the analog ground plane adjacent to the slot.

    On solid ground plane theory, high frequency currents tend to closely follow (are coupled to) source signals that cause them. As long as the source signals are routed away from the analog section, the resulting high frequency ground currents should remain closely coupled to the sorce signals and so will avoid the analog parts entirely without need for ground plane segmentation.

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  • Roibert
    replied
    I never did a measure, but this is my idea:
    Image we have a square GND plane . We can see it as a infinite resistor in parallel to each other,as I designed in attach
    file .
    Image from point P (on the rght) is generated some current . Example, the emitter of a transistor going to GND.
    The current from P to GND main (the connector) will distribute over all the parallel resistors.
    Or, in other term, beetwen P and GND Connector will be a Voltage V: any resistor in parallel will see this voltage and
    will create his current V/R.
    Of course the Resistor beetwen P and GND Conn will be less than resistor going from P-Analog -Gnd Conn, but not so little

    Maybe in HF, the inductance of long path will increase resistence and so, flow less current.
    So, in general, --I think-- the current will be distribuite all over the GND plane ..if we dont cut it.


    Roberto

    Click image for larger version

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  • robertferanec
    replied
    Roibert I would also try to do everything with one solid GND plane. The main question is, why the noise under FPGA should spread to the AD area? If properly designed, I believe the "noise" should stay in specific areas and it should not spread through the whole GND plane - if that is happening, then there is something not correctly done (?). But I do not normally design sensitive AD boards, so it would be better to hear a feedback from someone who is designing these kid of boards. Anyone?

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  • qdrives
    replied
    Well, a net-tie is just like a component.
    Two pads and a fill or track between them. The shape you make it, is up to you, but that is only the "joint" of the two nets.
    https://resources.altium.com/p/using...n-requirements
    I have created a net-tie for an antenna to prevent the Gnd plane to be called Antenna. The width of the pads matched the antenna requirements.
    Below is another net-tie, the same size as a track to create a Kelvin connection with Gnd. Oh, and this is for analog current measurement (max 70A)
    Click image for larger version

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  • Roibert
    replied
    Thanks for reply.
    I will follow the link and come back if some question.

    For now, somoone know if my question in post #8 is possible.

    Thanks again
    Roberto

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  • qdrives
    replied
    How sensitive is the analog input?
    How much current are you doing in the CPU?
    I design motor drives. Switching 20A and doing the current measurement (ADC). All with 1 single Gnd plane. My biggest problem is that the Gnd plane also has impedance and will 'lift' the single ended current measurement which needs to be compensated in software.

    I think you can proof it by doing simulation, but it would be cheaper just to build a proto and measure/test it.
    The noise on the Gnd plane can also been seen as crosstalk - https://www.youtube.com/watch?v=5EeQPxRdurkband https://www.youtube.com/watch?v=EF7SxgcDfCo
    Splitting plane: https://www.youtube.com/watch?v=52fxuRGifLU

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  • Roibert
    replied
    For qdrivers and Mulfycrowh.

    Thanks for your reply about the bad choice to split plane. Sayng the true, Im not a fans in spllitting ground plane, because some explain to me that, near the cut, born many problems with impedence. Apart this, in attach I send you a desingn with a very simple requirement ..read analog signal.

    How you wold positionate the AD and CPU in the PCB ? I will do as show in the design ,and separate with 2 GND plane.
    Do you think that with no ISO and only 1 GND plane, noise in analog is better ?
    Maybe can you suggest some tool for proof this (my dream ).
    Thanks
    Roberto
    Click image for larger version

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  • Roibert
    replied
    Last problem about net tie (top or inner) : last obstacle is that the geometry is fixed ..so the connection point must have the same geometry of the net tie components....of course, tipical of any components .

    There is a way to modify the geometry of a components in --real time-- on the PCB ? The best could be in a Polygon way ..
    I never see it, but maybe a miracle on the 22-02-2022 (:

    Thanks to all again

    Roberto

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