Power Pads!

[JohnsonMiller]

In modern DC-DC regulators or Battery charger chips, sort of pads exist that go under the package, mostly high power pins. A sample is shown below.
When connecting a trace to such a pin, if the trace is horizontal the cross section will not change so the current or Amp/trace will not change; otherwise, we use via under pad and make the vertical cross-section bigger. Even this is not feasible since those pins have small width and no room for normal vias.
What do you think, that this sort of pins are getting popular? Is it for increasing current or sort of heatsink?

[qdrives]

The current carrying capability of the pads is many times higher that the silicon and bonding wire have.
Often the pads are 0.2...0.3mm thick copper. Copper is also one of the best heat conductors / spreaders.

So if I look at your sample I would also say that it is both a reduction of heat (lower resistance) and heat conduction (partly heatsink).
Thermal vias do not do so much - https://www.signalintegrityjournal.c...-than-we-think

[JohnsonMiller]

qdrives, thank you for the comment.
My point is how to use these pins. Normally traces on the PCB are horizontal, this way cross-section for small pins and the bigger pins is the same, and the current flow won't change; otherwise, we use vertical trace, for the SMD part this means via-in-PAD, surely current capability will be much higher. Here the question is those long pins have a narrow width, how do you fit via under pad?

[qdrives]

All pads end on the edge of the chip. The max77960 is 3A/6A.
Looking at the block diagram we see 4 FETs (Q1, Q2, Q3, and Q4). I have drawn multiple parallel FETs in the footprint below.
As I mentioned before, the resistance (and inductance?) of the copper pad is probably lower than that of silicon and bonding wire.

Do you need vias? I would say no. Just keep the width of the track at least as wide (or should I say high?) as the pad is.

Width of the pads: 0.25 and 0.3mm. 35um final coppper thickness (1oz) with 3A, will give a temperature rise of 80°C.

The layout example in the datasheet only shows vias under the chip when they go to another layer.
Personally I would not place then in the pads.

[WhoKnewKnows]

You might consider how the IC mfg suggests to layout the PCB via their eval board ¯\_(ツ)_/¯
See page 15.

The mfg eval board isn't always the cheapest solution, but you can gain an ideal of what's important sometimes