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Impedance calculation

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  • Impedance calculation

    I am working with a reference PCB design. My reference PCB design is launchxl-cc3235s simple-link WiFi cc3235s dual band launch pad development kit. I have altium file of this, with reference guideline PDF​. It is said in the guideline of this PCB board that the control impedance is 50 ohm. It has a total of 4 layers. Image of layer stack-up is given below. I have done the impedance calculation for 50 ohm according to the layer stack-up of this PCB board in altium designer.​Here the trace width for 50 ohm impedance is 17mils. But in my reference design the maximum trace width is 6mils .​Now my question is where the trace width is 17 mils with 50 ohm impedance, why is 6 mils given in the reference design? It is normal that the trace width will be large in high current trace, but why did it give normal signal trace width 6 mils? why not 17 mils for 50 ohm impedance?

    Attached Files

  • #2

    Your stackup is for CPW 50 impedance matching.
    For CPW impedance matching the reference is not only GND plane but also on the TOP layer GND clearance of CPW trace with GND pouring.

    Click image for larger version

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    • #3
      The calculation is not for single ended 50-Ohm.


      • #4
        They say 15 (that is close to your calculated 17):
        Click image for larger version

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        • Shahriar sakib
          Shahriar sakib commented
          Editing a comment
          Thanks, but why is the reference design using 6 mils trace width?

      • #5
        6Mil traces are not impedance controlled traces. They may be GPIO. Not high speed signals.


        • #6
          Oh ...I understand now, no more problems, thank you​.