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Hole-to-Hole Rules for press fit connectors

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  • Hole-to-Hole Rules for press fit connectors

    I have a thick 5mm PCB with press-fit connectors on both sides, pads are full-stack and is top-to-bottom, pins on both sides have the same net, so electrically there is no problem. But when running DRC, I am receiving lots of hole-to-hole errors, I need the rule to inform Altium that both hole sets belong to the same net and it is ok to be placed on the same location, any help?
    I have already tried some options, but no success!

  • #2
    I think you might have to create a dual connector footprint. IE a footprint that has a 3D model connector on both sides.

    Perhaps in the schematic, every other connector will be a standard type so it shows up in the PCB design, and the others will appear the same in the schematic, but the type will be mechanical so they're included in the BOM but not expected to be part of the PCB circuit.

    Even if you get your current design to not have errors, I suspect there will be double drill hits on each hole. Plus too likely not to get the connectors perfectly aligned.

    Hope this helps 🤷

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    • #3
      Thank you for your suggestions and comments,

      - A footprint with a 3D model on both sides won't help, since we sometimes need to make connectors DNP, i.e. top mounted while paired bottom not mounted
      - I made connectors as mechanical, but no change still I am receiving errors. I am going to create a new part for back-mounted connectors, and remove pins.
      - This "double drill hit" looks serious issue, I was not aware of it. Are you sure that the manufacturer (or ALTIUM) does not process NC_DRILL files to remove double hits from drill data? Drilling a hole two times, considering the tolerance of drilling, can cause issues and the hole diameter will increase so the connecter does not fit properly.

      Another question, how can I make a component excluded from DRC? I have a special mounting hole, I know it has some violations, but want ALTIUM to ignore it.

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      • #4
        Do as in the below snap.

        Click image for larger version

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        • #5
          Thank you for your help, using your suggestions I managed to solve the Hole-to-Hole violation.

          There is a strange violation! In design, we have pads that are "direct connected" to planes. After running tools -> Split Planes -> Rebuild split plane on all layers, there is no violation on pads, but after running DRC, a large number of violations show up, here is the screenshot. Wondering what is the reason? Since I am seeing no violation then after a DRC run violation appears without any PCB change, I assume something is wrong with Altium. Looks like it does not save rebuild data, any comments?
          Click image for larger version  Name:	VIOLATION_GND.png Views:	0 Size:	89.2 KB ID:	21533
          Attached Files

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          • #6
            It seems you have placed multiple pads on each other. Also please check whether they are plated or not. TH pads has to be plated to be connected in inner layer.

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            • #7
              Abdullah Ansari, the design is a thick 5mm board with a press-fit connector on each side,
              Yes, we have to place TH pads on each side and they overlapped,
              I have also checked, and the pads are plated.
              Another point is that PAD-to-Plan is directly connected. The strange issue is that I am receiving errors not for all pads, just a few pads! But the erroneous pad has no difference from the next pad which has no problem.

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              • #8
                I would suggest instead of Plane use polygon pour. it might help.

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                • #9
                  But what do you think about the logic behind this error?
                  My suggestion, it looks to be a bug in Altium's DRC engine. If you check the error statement, it claims 0 sq. mm, it does not make sense!

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                  • #10
                    did you try to remove the via and place it back? it really looks like multiple vias on the top of each other (see the text with pin name) and that would show 0

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                    • #11
                      robertferanec, it is not via, but pads of two connectors one on top and the other on the bottom side of the board.
                      And the strange issue, I have many similar pads with GND plan connection, but only a few are included in the DRC report. If there is something wrong, I was expecting them all on the list.

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                      • #12
                        it is not via, but pads of two connectors one on top and the other on the bottom side of the board.
                        - ah. I am not sure then

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                        • #13
                          "Unrouted net" rule. So do you see all the pins connected on the plane layer(s)?
                          What if you would manually add a trace (ie. on the top) to connect the pads?

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