Please help me route xSignals normally. They are always only straight lines.

[chrislafave]

I had removed the routing from an OpenRex board and re-placed the components manually. I referred to the original for placement of the big chips: the MCU, the memory chips, and the headers. I intend to route it all within constraints (USB, PCIe, etc) and then re-do the placement. This first time I "updated" a blank pcb with the schematics, which puts the components of each schematic page on their own row. So I just placed them in that order, row by row, on top and bottom layers, until they all fit. Next time I will place them in the right order, getting to those decoupling caps early.
I have spent most of my weekend struggling to get the xSignals to route normally. By "normally", I mean as seen in the second image below, of the original board. I use the xSignal Multi-Chip Wizard, choosing "On-Board DDR3 / DDR4", 8 lines per lane, ~0.5mm tolerances, from the MCU to the four DDR3 SDRAMs.
The rules for both boards look the same, and the routing rules are in the third image below.
The outcome is the same with or without the BGA room.
Altium version: 23. OS: Win 10 (guest) on Linux host.
I have tried to solve every roadblock myself until now, using Google and Youtube, but this xSignals routing problem is not budging. I would greatly appreciate some advice. I will add more info if needed.
Christopher LaFave

[qdrives]

I only see one image with the rules...

[chrislafave]

Thank you, qdrives, for posting because I didn't realze that my post was there at all. I had deleted it but it appears that a version, in which I'd added the "rules" image, was restored.
I edited the post in question, restoring the original two images.
Since originally posting, it is my understanding that xSignals are just a powerful way to create a class comprised of multiple tracks that make up a current path. Even though autorouters are usually ridiculous, everything I'd seen of the xSignals Wizard until the post had looked like autorouting, but were actually already routed somewhere, somehow unmentioned. And the xSignals can be length-matched as a group by the xsignals wizard (e.g. in Mr Feranec's "Altium - How to use xSignals (in Fly-By, T-Branch + Other useful things)" at 03:10.) I have watched that video many, many times and, like with many of his other tutorials, I miss things if I don't pay super-close attention (and pause a lot and take notes) that I realize the next time I watch it.
On my next weekend (Tuesdays and Wednesdays) I will improve my xSignals skills a lot and hopefully have time left to start on ActiveRoute. I really can't get much done after work because my mind is mush from exhaustion, like right now. I hope you don't mind me having added all of this personal stuff.
I will eventually place and route this board or one of comparable density and make it fully functional. But that's probably after several more months to a year of busting ass.

[qdrives]

So if I understand you correctly, you expected X-signals to be like an auto-router?
From what I know, it just sets the rules for you. The actual layout is still (mostly) manual.

But, I have never used x-signals, nor do high speed designs. I was just missing the images.
Good luck on completing the board and if you still have questions....

[chrislafave]

Thank you qdrives. I'm sure we'll be speaking again here soon enough. Until very recently I had been working entirely alone because it takes a day or so to get an answer online anywhere. And I can only get this engineering stuff done on my days off. I get bone-headed after a work day and no amount of sugar really helps much. But I've reached the point at which I need to reach out.regardless. So I come back to Fedevel. Mr Feranec's super in-depth PCB tutorials are why I _will_ work as a PCB design engineer. Watching them has been like being an intern working next to a seasoned expert. (I wish I had done interning in university but still don't know how anyone found the time). I have a couple full notebooks of notes from his tutorials (and some interviews, such as with Eric Bogatin and Rick Hartley). I've probably rambled here again but I hope it's interesting.

[qdrives]

chrislafave Just an off topic remark - sugar is bad for you. You might be "bone-headed" because of it.

[chrislafave]

I spent this weekend (Tuesday, Wednesday) learning to route DDR. Attached are pictures of my length-tuned tracks of Bank0 using layer L8 , and Bank1 using layer 3 (just the data lines right now). The second image is of layer L8 only and the third is of layer L3 only. I had done Bank1 first, which is why the tracks are a little too curvy.
Next weekend I'll do the rest of the RAM data lines and then address and control. And finally use xSignals correctly after that. And then power will be my introduction to the PDN for RAM and the whole board and all of the power polygons. But power will be a couple weekends all by itself.

[qdrives]

I never did DDR memory layout, so it is best if others comment on this further.
One question though: why do you have the serpentine on all lines? Is it because it is easier to remove than to add?

[chrislafave]

If you're describing how the longest net in the class is left alone while the other nets in the class get serpentines to lengthen them, I believe that it originally was like that. I had worked on Bank1 and written one "Matched Lengths" rule for it. I think that the longest net's name in the PCB panel was "dark" with the others yellow and needing tuning. After matching them all I edited the rule's query to include all eight banks. I remember that subsequently I noticed that all of Bank1's nets' names were yellow again, so I length-matched those again in addition to matching those of Bank0. I haven't checked but maybe with them all in the query, only one net of the 88 nets is "left alone" and "un-serpentined". I'm going to route the rest of the memory today (it's my Saturday) and the one-of-88 might become evident.

[qdrives]

Yes, I would think that you try to route without serpentines as much as possible. However, It may be easier to remove serpentines than it is to add them as they require space.

[chrislafave]

I did it over with them as short as possible. But I had to make room between the straight parts of the tracks for serpentines, as I did on a few in second image. DRAM_D3 is the short one and I put serpentines in D7 until it matched, so its length is no longer highlighted, as seen in the third image.
I was getting lengths for matching to that were too long, so I reverted to one rule per DRAM bank rather that one query covering all of them, so one track from each bank is once again determined to be the shortest,

[robertferanec]

chrislafave sorry for late reply, I was travelling a lot. You are doing great. You can connect the pins first and then setup xSignals for length tuning. That may help.

[Paul van Avesaath]

not trying to be disrespectfull but routing like this "free handing" is not a proper way of routing ddr in my opinion.
getting the via's in on all pins of the ddr would be the first step otherwise you will go back and forward with matching all of the time. (not perfect example below. but it show sthe point i am trying to make.. by implementing the via's early you will not have an issue getting them in later on in your design..


try to keep your routing not all over the place, because there will be more signals and power planes to content with

route you address / ctrl lines first. then start with the DM/DQ/DQS because in most cases the adress lines cannot be swapped in the processor but you are able to switch with DQ pins within the byte group. (meaning DQ0,1,2,3,4,5,6, may be swapped between eachother like DQ,7,3,5,1,2,4,6,0 just relocate the signals on the processor side were needed. note that you cannot swap locations of the DQS pair and the DM pin) after you have done the initial planning then run the x-signal wizard and tune the lenghts
please note that addres/ctrl lines may be longer than Data group lines.. and datagroup lines can be different from eachother. at least for ddr4.

try and keep all the groups on a single layer. so address/ control lines on a single layer. this is harder because there are more signals. (but they run half the spee+d of the data)


and each Byte group on a single layer.


please do not do this

hope this helps.