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  • Naveen-Krishnan
    replied
    Yes Robert Feranec. Thanks for your reply.

    Leave a comment:


  • robertferanec
    replied
    There was only 1 ground plane dedicated to my PCB. At this time I thought of disregarding the violations thinking that its a bug in Altium.

    Secondly, during layout review my colleague told me add GND copper pours in the Inner layers to get Stripline trace and better impedance. Suddenly the NET Antenae via violation went away.
    Yes, that is expected behavior. In second example the VIAs were making connections between the two planes. In the first example, the VIAs were not doing any connections.

    Leave a comment:


  • Naveen-Krishnan
    replied
    Hi,

    I got the same Net Antenae violation on Vias. But fortunately I was able to find a solution. Here it goes

    Firstly, I added shielding vias surrounding a RF trace. The vias was given GND net. At this time I had the following stackup
    1. TOP
    2. GND
    3. IN1
    4. IN2
    5.PWR
    6. BOT

    There was only 1 ground plane dedicated to my PCB. At this time I thought of disregarding the violations thinking that its a bug in Altium.

    Secondly, during layout review my colleague told me add GND copper pours in the Inner layers to get Stripline trace and better impedance. Suddenly the NET Antenae via violation went away.

    I was because of insufficient GND planes in the PCB, Altium was showing Net Antenae violation (according to my case).

    Hope it helps someone.

    Cheers ! Bye.

    Leave a comment:


  • robertferanec
    commented on 's reply
    you are welcome

  • ican7
    commented on 's reply
    thank you for your help Robert.

  • robertferanec
    replied
    Fantastic! I do not really know if it's a bug in Altium (we normally dont have this kind of problems), important is, it's now ok

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  • ican7
    replied
    For some reason when I redone the DRC the net antenna issue dissappeared. I didn't do nothing but it comes back on and off... Would it be a bug in Altium?

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  • robertferanec
    replied
    I would have to see your PCB, but I would expect getting this kind of error when VIA is connected on 1 layer only. Double check if all your polygons have Net Name assigned. I am sure you can figure it out. Please let me know then what the problem was.

    BTW: try to check "Remove Dead Copper" when you double click on the GND polygon pour.

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  • ican7
    replied
    yes both top and bottom as well as the middle layers.

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  • robertferanec
    commented on 's reply
    On both sides, TOP & BOTTOM?

  • ican7
    replied
    They all have net name and connected to gnd net.

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  • robertferanec
    replied
    It looks to me like the VIAs have no Net Name. Double click on the VIA and check. You probably want to set Net Name to "GND".

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  • ican7
    replied
    please find the pcb.

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  • robertferanec
    commented on 's reply
    Please, could you also attached screenshot of the PCB?

  • ican7
    replied
    please find the screenshot Robert.

    Leave a comment:

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