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AREA clearance rule

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  • robertferanec
    replied
    Perfect

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  • gabrielcuellar
    replied
    YeeS, That's what I was looking for. Thank you very much Robert !!!

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  • robertferanec
    replied
    Here is the result (Don't forget, you need to disable the ROOM Rule created automatically: Design -> Rules -> Design Rules -> Placement -> Room Definition -> ROOMNAME and Uncheck "Enabled"). You can rename a ROOM, just double click on it.

    Click image for larger version

Name:	Altium room rule.jpg
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ID:	3980

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  • robertferanec
    replied
    Yes, try to create ROOM (Design -> Rooms -> Place Rectangular Room) and then Create a clearance rule which applies to the ROOM (I personally try to avoid using ROOMS as you need to make then an exception when you will be porting schematic, otherwise it will want to remove it - or it used to, maybe in AD16 they improved it)

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  • gabrielcuellar
    replied
    Yes, that is the problem between "Tracks". I was wrong to write "Nets" up to the post.

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  • robertferanec
    replied
    I think, I know what the problem can be. In your last screenshot it looks almost right ... the errors seems to me to be between TRACKS in the area under footprint. The rule is between the footprint and anything on layer 1, but it is not a rule for TRACK to TRACK under the footprint. For this, you may want to specify AREA (instead of using HasFootprint) or make the tracks thinner.

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  • robertferanec
    replied
    Ok, I tested it on my AD 16 and it works just fine. Here are the screenshots:

    Click image for larger version

Name:	1um clearance under footprint.jpg
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ID:	3971


    Click image for larger version

Name:	the under footprint clearance rule.jpg
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ID:	3972


    Click image for larger version

Name:	the rules.jpg
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ID:	3973


    Click image for larger version

Name:	the rule test.jpg
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ID:	3974

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  • gabrielcuellar
    replied
    Yes, I do, and no error but now I put the syntax HasFootprint('STM-LQFP100_N')OR HasFootprint('SOIC-28') to discard some error in the if it existed.
    Is there any rule affecting the nets of the rooms?
    How did I can apply?

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  • robertferanec
    replied
    Hmm, now, I do not really know Did you try the "Test queries" button?

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  • gabrielcuellar
    replied
    Yes, of course, I just think in this form to concatenate the footprints in one query, also try follow your advice but this have the same effect.

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  • robertferanec
    replied
    Can you post a screenshot of the whole U5 rule? Did you try to put there only the one footprint or you are trying to apply the rule on more footprints? It looks to me like in the rule you have something like "HasFootprint('STM_LQFP100_N', 'SOIC ....'". Hmm, I have never seen a rule like that, I would use OR between more footprints e.g. HasFootprint('XXX') OR HasFootprint('XXX'), .... Could you try it with one footprint only, if it helps?

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  • gabrielcuellar
    replied
    I run the DRC again but the violation over the nets around the component U5 disappear. But I try move the track and the violation appears again. The violation are by clearance between nets and between nets and pads of U5, I don`t know how show you only the violation over U5, but this screenshots help.

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  • robertferanec
    replied
    Please, find and select in the PCB Rules and Violations window only the U5 rule. Just to be 100% the violations are generated by the rule.

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  • gabrielcuellar
    replied
    Thank you for your reply Robert. I think the problem it´s in the first violation in the image for example one of many, there are so many violations, but I don´t care, for the moment.

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  • robertferanec
    replied
    Hello gabrielcuellar. Please, can you run DRC (Tools -> Design Rule Check -> Run Design rule Check) and then when you are in the PCB, click on the "PCB" button in the right bottom corner, select "PCB Rules and Violations". Please, browse the Violations and post a screenshot of the PCB Rules and Violations which you think are related to the problem.

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