Visual component causing violations

[angelsix]

Thanks that did the trick

[robertferanec]

We normally set a Component Clearance rule (Design -> Rules -> Placement -> Component Clearance) to ignore collision of the two (or more) components. See this screenshot as an example between PCIE mini card model (CR1), connector (J13) and other accessories:

[angelsix]

I am adding a purely visual 3D model to my design so I can see an mSATA board connected and in place.

I've made the 3D model, then made a helper outline on mechanical layer 15 so I can position the 3D model in the PCB design.

However, when I put the model anywhere that touches another it causes a violation of clearance.

How do I make this component ignore contact with other components causing an error and making the entire thing go green?

I've tried making the compoent Graphical and Mechanical and that doesnt help. I've tried other layers too. Nothing fixes the green color once they touch.