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Thermal Vias in Altium

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  • Thermal Vias in Altium

    Hi to everybody,

    I am trying to design thermal vias for a QFN package, but when i place them, i go to the PCB and they cause violations between the central pad and each one of the vias. So, how could i do it? (i am going to add some photos, for a better understanding of this).

    And i have another little question, i'd like to do tenting on the vias but not completely, only on the hole and the less possible part of the pad. How could i do it in Altium?
    Last edited by Jorge; 10-18-2015, 07:20 AM.

  • #2

    1) Check if VIAs have net assigned correctly - they need to have the same netname as the pad.
    2) You can adjust mask directly in the footprint library - just go on the Solder layer and draw it as you need.


    • Jorge
      Jorge commented
      Editing a comment
      Thanks Robert,

      1) They have asigned NoNet in the Library, it will be automatically correct, when i'll have connected in the PCB the vias and the bottom pad with the same net?

    • robertferanec
      robertferanec commented
      Editing a comment
      I am not sure if it will automatically connect. We normally do no place the VIAs into library as during layout we may need to move them.

  • #3
    Ok Robert Thanks, it has sense. For 2) How could i do it? (i add a photo to show what i have done). The top solder layer is used to mark the space not covered by the solder mask, right? So i have used a ring, to do a partial tenting on the via's pad, covering the hole to avoid solder wicking(inside of the via, and reducing its thermal efficiency). Does it look correct?

    I think that it can be done for a complete tenting, just clicking at "Forced tenting on top layer", right?
    Last edited by Jorge; 10-19-2015, 09:32 AM.


    • #4
      We simply do not mask VIAs under EPAD. If you are worried about tin flowing into it, maybe you can make the hole smaller and use more VIAs?

      If you are not sure, try to find recommended land pattern for similar EPAD and similar thermal requirements. What I am thinking about, if you make the mask around the VIA under EPAD, I am not 100% sure if the small mask will stop tin flowing inside the VIA. During soldering, very small mask can be damaged or tin may flow over it because of metal on the EPAD. Also, I think only a small amount of tin will flow inside the VIA and I don't think it will reduce thermal efficiency - tin also will conduct the heat. But that is just my theory ...