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General questions Net Class and Update Schematic

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  • General questions Net Class and Update Schematic

    Hi everyone,
    I have some basic questions about Altium.
    Firstly,I defined Net Class like this:
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    But if I clic on the Net USER_LED in the PCB windows, it goes automaticly to the position of the net but my net is not highlighted:
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    Second question,
    when I go to Design->Update schematic, I got this message that I don't really understand how t can I avoid it:
    I understand there are some problems with my components, generally I do my schematic and then do Tools->Annotate Schematics Quietly, is that the good way?
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    Then, I have like 4 Objects add corresponding to Rules of each sheets? It is these 4 red bloc but I don't know what it is for, so I remove it all the time.​
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    And finnaly, I have two side on my PCB, one for low pwoer and one High power. If I want to route the high power with a width 1mm clearance 1 mm and low power 0.2mm width and clearance, I should create a Net class and add then in my Design->Rules for each Net Class?
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    Thank you very much all these precious informations.

    Alex

  • #2
    I will try to briefly answer to your questions (I don't have much time since I am at work). Hopefully that will give you some tips, so that you can google the particular topics further if necessary.

    To highlight nets in the PCB you normally use the PCB panel, not the Navigator panel. I am not even sure if it's supposed to work with the Navigator. The Navigator you normally use for working with schematics. Make sure you have the highlight mode set on top of the PCB panel (mask/dim).

    Annotate schematics quietly is the simplest option which is quite quick, but doesn't give you much information about the changes being made. I normally use the Annotate Schematics option. Then you can see what is changing in the engineering change order (ECO) generated. However, the notification you are getting is usually something different. It often appears if the unique IDs of some components change. The UIDs are used to match the schematic symbols to the particular footprints in the PCB. The safest way is to go to Project -> Component links and to manually fix the broken links. This could be a little confusing at first. Normally just clicking Yes will fix the links automatically.

    In the majority of the cases you don't need Rooms. You can disable them in Project - Project Options - Class generation column.

    Your plan about the high/low power routing seem right.


    ​

    Comment


    • #3
      Thank you very much to mairomaster. I am adding some screenshots:

      1) You need to select MASK or DIMM in the PCB pannel, Normal will not do any changes.
      Click image for larger version

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      2) Go to your PCB and Project -> Component Links. Usually just press "Perform Update" works, but in some specific cases you may want to make the pairs between Schematic symbol and PCB Footprint manually or use Add Pairs Matched By: Designator / Comment / Footprint (all checked). As mairomaster explained you are getting this error because altium can not pair your schematic symbol with particular footprint (usually it is because for some reason symbol and footprint have different ID e.g. if you updated schematic with a new symbol for a component which already existed in PCB)
      Click image for larger version

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      4) If you like, you can define track width for specific nets. Here is an example of the rule: http://www.fedevel.com/designhelp/fo...ack-width-rule

      Comment


      • #4
        Thank you very much,
        It's really helpful.
        A question about your example:
        Click image for larger version

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        It's ok just but in this case you define the width for Power port (VIN,5V,3.3V,1V5_DDR...), but what happens if I want to route all the sheet called "High Voltage" with the same Width. In my example I want to route all my high power side with 1mm width, not only the HV and GND_HV:

        Click image for larger version

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        And finnaly, quick question, I saw in your example you defined a Width Rules for DiffPair_DIFF_90, why you didn't define it in the section "Differential Pairs Routing " below?

        Thank you very much


        Comment


        • #5
          1) I would maybe call all the HV nets with HV_ preffix. Then you can create a rule like InNet('HV_*')
          2) It's for compatibility with old Altium (some time ago it was not possible to define Diff Pair width inside Diff pair rule, it had to be done in a separate rule)

          Comment


          • #6
            Perfect thank you very much

            Comment

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