About Nets with multiple names

[mulfycrowh]

Hi everybody !

I have 3 sheets (see attached photos)

1/ Flash
2/LPC43572
3/ Hierarchy including the sheet symbols : Schematic

Considering the harness "EMC_FLASH", I have got many and many warnings about EMC_A16, EMC_A17 ... EMC_A21, EMC_BLS0, EMC_BLS1 ... EMC_BLS3, EMC_CS0, EMC_CS1 ... EMC_CS3.
In fact everything that refers to a bus.
Furthermore, I have also got a warning about NAND_FLASH_READY. This label is used twice in Flash : one time in the harness (as you can see it in the attached file), one second time it is tied to another component.

Is there any issue or should I skip the warning ?


​Thanks for your help.

HAPPY NEW YEAR !!!!

[robertferanec]

Hmm, I do not use harness, so I am not sure if I can help you with this. I saw in your email, that you see also "Net has multiple names" warnings. This usually happen if one net has different netnames - e.g. many times you can find this on AGND + DGND .... if they are connected together. Sometimes this warning can be found if you call signals on one page by one name, on the other page different names and you connect them together in the top sheet (so, when you use a hierarchical connection). But it looks right in your pictures, so I am not sure.

​Maybe someone who uses harnesses could help? Please mairomaster do you use harnesses?

[mairomaster]

A screenshot of the warning might be useful.

I normally don't use busses in harnesses - I don't quite remember, but I might have had some issues with that in the past. I know that it is neat and convenient, but Altium behave a bit funky once you start mixing up advanced wiring features. If you can't figure out how to fix t he warning, just check if the connections are physically made with the Navigator and if they are, you might just ignore the warnings.

[MadhuWesly]

@mulfycrowh Facing the same issue in creating Harness connectivity got many warnings:

Please let me know if you could solve this issue previously.

Is there any issue or should I skip the warning?
Will it be okay if a net is being named multiple when using Harness connector, signal, and entry?

mairomaster, find the description(not clear in screenshot) of warning:

Details

Nets Wire RADIO_GPIO_1 has multiple names (Net Label RADIO_GPIO_1,Net Label RADIO_GPIO_1,Net Label RADIO_GPIO_1,Sheet Entry U_Breakout-RADIO_GPIO.RADIO_IO_1(Passive),Sheet Entry U_RADIO-RADIO_GPIO.RADIO_IO_1(Passive),Sheet Entry U_SouthSide-RADIO_GPIO.RADIO_IO_1(Passive))
Details
Wire RADIO_GPIO_1
Net Label RADIO_GPIO_1
Net Label RADIO_GPIO_1
Net Label RADIO_GPIO_1
Sheet Entry U_Breakout-RADIO_GPIO.RADIO_IO_1(Passive)
Sheet Entry U_RADIO-RADIO_GPIO.RADIO_IO_1(Passive)
Sheet Entry U_SouthSide-RADIO_GPIO.RADIO_IO_1(Passive)


Thanks in advance.

[Raza Parvi]

Greetings everyone, I was able to resolve this issue of multiple names in a hierarchical design by unchechecking the "Allow Sheet Entries to Name Nets" in Project Options settings.

Please follow below steps:

From main menu bar select
Project -> Project Options -> Options
Uncheck "Allow Sheet Entries to Name Nets"
-> OK

Compile the schematic again and the warning should be no more there.

Thanks.