disconnect vai and pad in inner layer

[Baneshat]

Hi Robert
I have multilayer PCB project, that it was created power and GND plane and in the Rules plane clearance is 0.3mm define.
when I use via or pad with Holes and Diameteres of different sizes,
some of the Vias and Pads according to their holes and Diameters, not disconnect of Power and GND plane? while its should not connect to power and GND plane, because its vias or pads related to other signal.
See the figure below that shows the layer VCC.
look this vias and pad carefully:
Point A= Hole size =0.3mm and Diameter= 0.6mm
Point C= Hole size =0.4mm and Diameter= 1mm
Point B= Hole size =0.7mm and Diameter= 1.6mm
None of these should be connected to VCC plane. While Point C and Point B , apparently connected to VCC plane.
What do I do to solve this problem?
Thank you.

[robertferanec]

Press SHIFT+S go to Single layer mode. You will see only the active layer, that should help you to get better view on the layer.

[Baneshat]

I have done this,but unfortunately I did not understand it.
If possible, explain more.
Thank you

[robertferanec]

When you are in Single layer mode (SHIFT+S), click on the plane (it will be select) and it will look like the picture below. You can see which VIAs / PADs are connected and which are not connected to the plane (the VIAs and PADs with black circle around the brown circle are not connected ... the brown circle is hole)

[Baneshat]

Dear Robert
I am very grateful for your answers and guidance.
But, I think I could not make my own question well.
For this purpose, I will put the question to another form.
Figure 1 show the power plane layer in normal display mode(In other words befor shift+S) and figure 2 show the power plane layer after shift+S.
In the PCB are highlighted the three via with features:
Via1 : Hole size= 0.3mm and diameter=0.6mm
Via2 : Hole size= 0.4mm and diameter=0.8mm
Via3 : Hole size= 0.4mm and diameter=1mm
As you can see in the figures, the via 1 & 2 are Gap (clearance) of the power plane.
But seems the via 3 not gap (clearance) of the power plane.
Does via 3 cause problems?
Beat regards.

[robertferanec]

In the screenshots you are showing multiple active layers. From that view it is hard to say what is clearance on that particular VCC layer. For example, if your VIA has big pad on the top and bottom layers and smaller pad inside PCB, you can not see it. You need to use SHIFT+S or only show VCC layer.

[Baneshat]

do you mean that via has big pad on the top and bottom layers, is smaller in the inner layer?
In other word, via 3 that is show in the figure below not connect to the VCC plane?

[robertferanec]

Baneshat, I do not know, it is very hard to say from the view, but it is possible. Try only enable the VCC layer and check it.