Hi Everyone,
I am confused with a hole in pads and a bare via. The confusion comes from the layout of a SOC with thermal release pad, where vias should be placed according to the layout recommendation from the datasheet as seen in the attachment (The first figure).
What will be the differences between placing pads with " multiple layers" (the third figure) and connect to "GND" Net, and just Vias through the board and connect to "GND" Net (the second figure)?
Thank you very much,
BF
I am confused with a hole in pads and a bare via. The confusion comes from the layout of a SOC with thermal release pad, where vias should be placed according to the layout recommendation from the datasheet as seen in the attachment (The first figure).
What will be the differences between placing pads with " multiple layers" (the third figure) and connect to "GND" Net, and just Vias through the board and connect to "GND" Net (the second figure)?
Thank you very much,
BF
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