Asking about DDR3 Fly-by Topology Matching Length

[CamDoan]

I am doing with 88F6820 produced by Marvell (which the datasheet attached), in page 72/163 we have a photo 1 blow. The photo is about Fly-by topology matching length, but i can't get it clearly.
For example: We have address bus DDR3.A0, DDR3.A1.... As the photo below, do we have to matching length: (DDR3.A0.TL4 = DDR3.A1.TL4 =.... AND DDR3.A0.TL41= DDR3.A1.TL41=... this way is so hard to layout) OR JUST: (DDR3.A0.TL4 + DDR3.A0.TL41 = DDR3.A1.TL4 + DDR3.A1.TL41 =...)

[robertferanec]

The goal is, that all signals need to arrive at the same time to the first chip ... then all signals need to arrive at the same time to the second chip ... then to the third chip. So, the distances need to be the same for all signals. Also, you may need to keep TL41 short and the same length on one signal and between connections to all the memories (so these stubs are short and same on one signal). I do not think you need to keep A0.TL41 = A1.TL41, however you need to keep A0.TL42 + A0.TL41 = A1.TL42 + A1.TL41

If you have access to reference design, you can measure it there. Just be careful, the first segment may be different as you may need to consider length in package.