Hi,
I am currently designing a board based on the i.mx6ull 14x14 evk and have selected a 1GB 16 bit memory chip (MT41K512M16HA-125). I have followed your video about simulating DDR3 in sigrity and it was really easy with this video.
The problem I have now with the simulation is that I have hold time violations for all the data lines. I think this is because the length of the data lines is shorter than the address and clock lines. I matched the DQ signal to the data byte. And all the other signals to the address and clock.
I think this should be able to be compensated by write leveling calibration, but I want to make sure this is the case. Is there any way to add write leveling to the simulation or do I have to calculate the timing manually?
Corné
I am currently designing a board based on the i.mx6ull 14x14 evk and have selected a 1GB 16 bit memory chip (MT41K512M16HA-125). I have followed your video about simulating DDR3 in sigrity and it was really easy with this video.
The problem I have now with the simulation is that I have hold time violations for all the data lines. I think this is because the length of the data lines is shorter than the address and clock lines. I matched the DQ signal to the data byte. And all the other signals to the address and clock.
I think this should be able to be compensated by write leveling calibration, but I want to make sure this is the case. Is there any way to add write leveling to the simulation or do I have to calculate the timing manually?
Corné
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