Announcement

Collapse
No announcement yet.

Length matching in iMX6 Rex

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • Length matching in iMX6 Rex

    Hello Robert and everyone who are studing from iMX6 Rex project,

    I have question about the length matching for signals in DRAM_ADDR_CTRL group. I draw something how the signals are routed, please see following picture


    Length of signals on Layers are L1 (for Layer1), L2 (for L2) v.v...
    Length of vias are H1, H2, H3, H4, H5,

    The rule is the length of signals in DRAM_ADDR_CTRL group for TOP DDR3 and BOTTOM DDR3 must be same length or similar length. As we can see
    the Length of signals for TOP DDR3 = L1 + H1 + L2 + H2 + L3 + H3 + L10 + H4 + L1
    the Length of signals for BOT DDR3 = L1 + H1 + L2 + H2 + L3 + H3 + L10 + H5 + L12

    The value " L1 + H1 + L2 + H2 + L3 + H3 + L10" is the same for 2 DDR3, but the lengths H4 and H5 are differently (maybe H4 > H5). So, my question is "must we take care the length of vias (H4, H5) when calculate the length matching for signals? Is it effect to the length of signals and can we skip H4, H5?"

    Please clarify for me

    Thank you,
    Tuan
    Attached Files

  • #2
    Hi
    tuandt
    Junior Member
    tuandt, yes, you should take that into the length matching consideration. That is one of the reasons why we normally length match ADDR/CMD/CTL signals more precisely than specified in design guide, so we are sure, that even if the difference between H4 and H5 is applied, the signals in the ADDR/CMD/CTL group are still routed withing the required tolerance.

    BTW: If you use the xSignals, you can nicely see that difference, I pointed it out in this video: Altium – How to use xSignals ( in Fly-By, T-Branch + Other useful things )

    Comment


    • #3
      Hi Robert,

      Thanks for your answer.

      Comment


      • #4
        Hi Robert,

        More one question, I read the design guide for imx6 chip. I understand that the length matching is for each of groups (DATA, CLOCK v.v...) with one DDR3 chip. So, my question is "Must we make sure the length of signals are matching between 4 DDR3 chips (in imx6rex project) with T-branch topology?". As i know, in fly - by topology, the length matching between DDR3 chips aren't necessary.

        Thanks for your support,
        Tuan

        Comment


        • #5
          Must we make sure the length of signals are matching between 4 DDR3 chips (in imx6rex project) with T-branch topology?. As i know, in fly - by topology, the length matching between DDR3 chips aren't necessary.
          What signals do you mean? If you mean ADDR/CMD/CTL, they are placed in the same distance from CPU to keep T-Branch tracks balanced, so the signal quality in T-Branch tracks is the best. Or by the other words, from controller point of view, you are right, they do not need to have the exact length, but from signal quality in T-Branch - keeping the lengths same creates the branches the way which gives you the best quality of signal in the points where the memory chips are placed. If you place them differently (in un-balanced T-Branch, when the distance between CPU and memory chips is different), the signals can get messy and the memory chips may not work properly.

          Comment


          • #6
            Hi Robert,

            Thanks for your answer.

            The signals that i prefer are ADDR/CMD/CLOCK like you said.

            Comment


            • #7
              Hi @robertferanec,

              I think i will continue this thread with another question relate to imx6rex project that need your help. I saw that in pcb of imx6rex project, some signals use Vias from L1 to L12, but the route is in L1 and L8. Seem the signals have a stub that equal length of L8-L12 and in high speed design has a rule doesn't make the stub for signals. So, could you clarify for me?

              Comment


              • #8
                At the DDR3 frequency those stubs don't really matter. Using through-hole vias cuts down the manufacturing cost of the board and makes the board more simple than using many stacked vias. I am not sure if there was another reason as well.

                Comment


                • #9
                  I agree with
                  mairomaster
                  Junior Member
                  mairomaster. Normally, if we can choose (e.g. if we use uVIAs and Buried VIAs) we may use the better VIA option (e.g. use uVIAs if going from L1 to L3). If we only use through hole VIAs, there is not much to choose from. However, we have routed a lot of peripherals with through hole VIAs only and VIA stubs were no problems - they are all working fine (including DDR3 memories). Be careful, if you go for higher frequencies (e.g. above 5GHz), you may want to think about it.

                  Comment


                  • #10
                    Hi,

                    Thanks both of you. I had the same think like you but i need more clarify from the most people experience

                    Tuan

                    Comment

                    Working...
                    X