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IMX6 IPU Display Clock Configuration Help

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  • robertferanec
    replied
    It will depend on what software you are using, but here is an example how we changed clock in Kernel 3.0.35. Maybe it will help you (check out the arch/arm/mach-mx6/clock.c): https://github.com/FEDEVEL/imx6rex-l...7671698d88197d

    Leave a comment:


  • ranaya
    started a topic IMX6 IPU Display Clock Configuration Help

    IMX6 IPU Display Clock Configuration Help

    Hi All,
    I am having a trouble setting up the the clock rate of IPU1DI0 of IMX6Q. Currently the parent clock of IPU1DI0 is set to PLL5_vid_dev (76MHz), and the clock divider being 2 (38MHz) according to clock summary result. I want to bring this IPU clock rate to a lower value (to interface with a low resolution LCD - pxclk of 27MHz), by increasing the clock divider. I am aware that the relevant value should be written to CCM_CHSCCDR (base+0x34) as per IMX6QRM, but where do I need to make the changes (in U-boot or kernel and what are the source files) ?

    There is this parent clock assignment line in clk-imx6q.c :
    clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider(“ipu1_di0_pre”, “ipu1_di0_pre_sel”, base + 0x34, 3, 3);

    imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
    imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);

    If I'm not mistaken, the imx_clk_divider should return the divider value. But here how the divisor is determined ? I don't want to change the parent clock, but to change the clock divider to 3 ! Specifically what do 3, 3 parameters passed into imx_clk_divider() mean ?

    Thanks in Advance
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