Different suggested Stackup

[avion]

Hello,

After placing all components and some RAM routing I wanted to make sure the stackup config that came with the lessons was achievable. So I asked Exception PCB Solutions (same manufacturer) but the guy said;

"Thank you for your quick feedback but I am sorry, it is very risky option to go with the current stack up as the microvias 2-3 drilled at 0.1mm through 0.11mm dielectric is not liable option as this exceed our plating aspect ratio for blind vias : 0.8 :1. The consequence is high probability of voids inside of microvias after plating.

For that reason, I cannot meet the current stack up which provided by my colleague in 2013."

The stackup that he suggested comes with different via hole and track sizes, see attached 2017 version. Would this make my design harder and should I push for a different manufacturer with higher microvia aspect ratio? Or should I go with this stackup?

[robertferanec]

We keep manufacturing the iMX6 Rex PCB through them, no complains

PS: I would not be surprised if he is actually trying to force you to make the stackup easier, so they can use cheaper Chinese company to manufacture it. The stackup he suggested has completely different impedances (e.g. Target impedance 100OHM, calculated impedance 94OHM). Also, his stackup shows stacked uVIAs, I am not sure if that can influence something.

[avion]

layer 4 and 9 are not used for signals but only for GND however in the 2017 stackup the config is based on them being signal layers. Do you think this influences the overall impedance control of the stackup?

Does stacked uVIAs mean I have to go directly from 1-3 instead of 1-2 then 2-3? They also appear filled in this case is there any significance compared to just normal plated?

[robertferanec]

layer 4 and 9 are not used for signals but only for GND however in the 2017 stackup the config is based on them being signal layers. Do you think this influences the overall impedance control of the stackup?

- Definitely. Also they change thickness of dielectricum.

By stacked VIAs I meant, they placed VIAs on the top of each other. Normally I do not place VIAs on the top of each other as it makes PCB more expensive.