No announcement yet.

Hole to Hole Clearence

  • Filter
  • Time
  • Show
Clear All
new posts

  • Hole to Hole Clearence

    My manufacturer has specified different stackup from the one shown in the lessons. Luckly all trace widths in all layers are in compliance. I would like to make sure I can make this pcb in full compliance to them. So I obtained their Design for Manufacturing (DFM) guidelines. Theres a lot to look for in there. I would love to watch a video explaining these by Fedevel. Anyhow, I think one of the most important rules by manufacturer is the hole to hole distance and they specified it to me as follows;

    Hole to hole are subject mechanical or laser drill and to be or not on the same net.
    Mechanical drill:
    On the same net : we advise minimum 0.15mm.
    Different net : Outer 0.2mm, and 0.3 for inner layers.

    Laser drill:
    On the same net : we advise minimum 0.1mm.
    Different net : Outer 0.15mm, and 0.2 for inner layers.

    I cant figure out how to do this for each layer and for specific vias and same nets in the design rules of altium. Could you give me an example??

    I have also many violations in PAD to ALL clearance rules at 0.1mm. Can I simply ignore this if my via pads are not touching and if my vias meet the hole to hole clearance.

  • #2
    Normally this is not a problem in design. Usually when you for example use standard small VIA like 0.45mm diameter / 0.2 hole, then even if you place the VIAs the way they would be touching, the distance between holes will be 0.45mm.

    So the problem is mostly about VIAs in same net (e.g. VIA array in Exposed pad) or if you are creating non plated holes (they do not have ring around them, so it may be easy to place them close to each other).

    If you need you can set specific rule in Design Rules -> Manufacturing -> Hole to Hole clearance
    For the VIAs in pad, I think you may use Design Rules -> High Speed -> Vias under SMD (I am not 100% sure, you can try, let me know )