OpenRex DDR3 Memory Interface - A14

[schad.rio]

On pg3. CPU DDR3, DDR3 Mem of the OpenRex schematic, I notice that pin A14 is not grouped with the other address input pins but instead with the NC pins. I understand the processor supports up to a 16 bit bus and this particular DRAM (256Meg x 16) supports up to 15 bits for the row addressing (see attachment). Why is pin A14 grouped separately from the other input pins and not labeled as an input ?

[robertferanec]

No special reason. The original symbol was for smaller memory and A14 was added later.