I have started to design an FPGA board and as first step I am trying to create the schematic for the XC6SLX9-2CPG196C chip. I would like to do it in separate banks. I have created a schematic library for each bank, but I do not know how to combine these banks in one single footprint.</br></br>Any help would be appreciated. If the question is unclear feel free to DM me to discuss.</br></br>Thanks.

For example, when I add these separate libraries to my Schematic and import the changes to PCB, I am seeing one chip for each library. Which is actually what I was expected. However, I do not know how to combine them.

I think what you mean is that you want to create a multi part symbol.</br>https://resources.altium.com/p/your-altium-library-multiple-part-symbols-ease-your-design-time

Was just about to answer same. Yes excatly, you mean problably multi part symbol.

I also have tried that solution. However, this time when I drag the Multiple Part Component from the component library, only the Part A is shown. I can not reach the other parts.

Oh okay. I found it now. When a multiple part component is selected, its parts can be reached from the models section below.

Thank you for your help @Mini , @QDrives . Wishing you a good day. 👋

Also, dont forget to give it the same reference designator .... U1A U1B U1C ... means they are all U1 component

Yes the main designator is set as U1 and Altium automatically adds the part name to the component. So, Part A comes as U1A. Thanks @Robert Feranec

Hi @Robert Feranec I am a pcb layout engineer and I have a question, can I give a polygon in between the two PCIe4.0 differential line? Because I cannot find any answer over the internet. I followed most of the layout guidelines of the PCIe4.0. And I have lots of space on the board to give ground polygons.

Do you mean to place copper (polygon) between two differential pairs?</br>Yes, if you add sufficient stiching vias. Do note, that the impedance my change a bit due to the additional copper.</br>And do not forget about copper balancing.

The thing is For PCIe4.0 5W clearance is required and the board is of 24 layers so I have plenty of space in other layers majorly on differential routing.

Yes and those differential pairs have 8 GHz of signal speed as per the PCIe4.0

I forgot to mention that Robert made a video with Eric Bogatin, but I do not know exactly which one. Perhaps this one:

https://www.youtube.com/watch?v=U60y4JC0Wxs

Thanks I hope this works, and also it will provide copper balancing in my pcb

So this series was a nice cheap one but it is still viable this year or is it just not practical since it is sort of old?</br>Also i did not design the daughter board yet not wrote toe Verilog , would writing that down first help with /ic selection? </br>my design is not that complex and i only need to output like 4 precise PWMs and maybe a serial + some I2C/SPI data to be read from the motherboard ADCs....?</br>Is there another series i should look into that is sort of beginner friendly wit free dev tools?

ICE40 FPGA is definitely good place to start even in 2024. What series, daugther board you are talking?

i was thinking of the olimex board and the motherbard will be my design

What olimex board? What are you tring to achieve?

since i want to use the FPGA as a controller, and compare with a few MCU maybe

Im pretty sure you don't need FPGA for that.

i am considering buing this: https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware

well it is more like to compare how it done not in be woth in $ then again ice40 is MCU lvl cheap

like c++ vs verilog up to a point would be a nice thing to try

then again i am studding dual active bridges and i am not sure what would be easyer to implement since i didnt not find much about actual compensation and controll input frequncy

I don't know about the board, but it's definitely cheap. I personally don't like the design.

Was wondering about the verilog part. Usually Europe seems to use VHDL.

well my skills are basic at best and i have a few friends with work with verilog so i can ask there

Anyway if you are looking information about FPGA visit "nandland.com". He has a lot of information about FPGA in verilog and VHDL. He has his own development board and he is using ICE40k as well. A lot of projects there. He also recently published whole book about FPGA.

a low of PWM sincronised on a MCU seems scary to code so that is why i am considering a cheap FPGA

i know that nandland i saw some tutorials and it was manageble, that is why i am considering this chip and verilog

and well ultimately i want to integrate all in a single PCB but untill then with aproach where i can switch the controller is ok since i am not sure how well stuff will work with the MCUs +no scope at home so haveing the digital logic signals on display on a fpga virtual test bench will help a lot

I don't see a reason why you can't do that with MCU, you can output PWM with MCU as well. But you can always try with FPGA.

well phase shifting them seems hard atm ( only at HW design stage) also i am not sure i can get good enough resolution at 100-500kz

hello , can someone explain to me what's the meaninge of "routing signals with FPGA"  with multiplexrs for exemple.

i think it meand using an FPGA as a MUX. so you have input signals on it and output signals on it, lets say 8x8 then you have the possebility to create any input/output path connection.

Hi @karimoviç ,<br>FPGA as a device is different than Microprocessor or Microcontrollers.<br><br>Essentially it is a blank white board and you can create any logic that you want inside and FPGA.<br>"Routing signals with FPGA" without the context can have various meaning out of which one is highlighted by @Paul van Avesaath <br><br>But in FPGA when ever you design a logic you actually route a signal physically like all the parameters that are associated with a physical copper trace apply to the FPGA routing and all the signal delays must be accounted for...<br>So "Routing" in FPGA means Routing in its literal sense..<br><br>Thank you.<br><br>

For "routing signals through FPGA", I would rather recommend to use a CPLD (FPGA usually has to be loaded after start, CPLD is programmed and then works). This technique is usually used for something where you would otherwise need many Gates or Logic chips to get the behavior you need (and very often it is used to generate chipselect). Also, if you use CPLD (instead of doing it through chips and routing) you can re-program the behavior - eg. in case you make a mistake, you can change it (that would be hard if you would chips and route it on PCB - you would need a new board version, with CPLD you just update the firmware).

The OP needs to provide more details. Routing <b>within </b>FPGA is the process by which the logic resource (mainly logic gates and flip flops) are physically connected together using the routing resource. This makes it possible for electrical signals to travel between the logic components that implement all the combinatorial and sequential functonality of the design. The routing process is carried out automatically during the floorplan stage of design compliation, this step follows the design synthesis stage where the design usually described in an RTL description in HDL is converted into a netlist.

I am having trouble getting ModelSim up and running to support some HDL work that I have been doing. It is likely the result of operator error -- I used ModelSim for some Xilinx based projects a few years ago so I have some familiarity, but am brand new the the Altera/Quartus environment and am definitely rusty when it comes to the process so I appreciate your patience.<br><br>For starters, I am getting an error when running ModelSim on a clean bladeRF project (hosted, 115KLE). After cloning, building, and opening the project in Quartus, I run the RTL Simulator and see the following log output once ModelSim launches:<br><br><div class="bbcode_container"><div class="bbcode_description">Code:</div><pre class="bbcode_code" style="max-height:calc(30 * 1.4rem + 2 * var(--bbcode-padding) + var(--h-scrollbar-allowance));">// other stuff # -- Compiling architecture hosted_bladerf of bladerf# ++ Error: (vcom-11) Could not find work.bladerf# ++ Error: ~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd(27): VHDL Compiler exiting# ++ Error: ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.# Error in macro ./hosted_run_msim_rtl_vhdl.do line 68# ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.# while executing# "vcom -2008 -work work {~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd}"ModelSim&gt;</pre></div>As I mentioned this is on a stock project, so I suspect it could be a configuration or path problem. I know the *_tb.vhd and *.vho files are spread out throughout the project tree, so is there a certain directory I should be in when doing this? Once I get up and running with these stock bladeRF testbenches I can apply that configuration to my own application. Please let me know if I can provide any additional information. Thanks!<br><br>And I've been asked by a friends dad about what to get his son as a beginner electric. I've always thought Yamaha Pacificas (I read <a href="https://bestelectricguitars.reviews/best-electric-guitars-under-500/" target="_blank">article</a> about it) to be fairly consistent. Do you agree or got any other ideas?<br><br>Thanks for any help given.

Not really my area <img src="https://designhelp.fedevel.com/core/images/smilies/frown.png" border="0" alt="" title="Frown" smilieid="11" class="inlineimg"> Can't help. Maybe someone else?

<br>Hi <b>@Giayniod,</b><br>Is that file located on the given path?<br>/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd,

Hello @Giayniod ,<br>For Model sim to work you need to Start with Change directory first and locate the directory where your Test bench file is kept in your computer.<br>Then you go for creating library for simulation.<br><br>Thank you.

I have been trying to install xillinx 14.7 but it keeps showing error but I have a project to submit in like 16 hours. So any online tool which can help me get my results asap I need it for my project about <a href="https://maybeloan.com/payday-loans/mi" target="_blank">online payday loans in MI</a>?

Hi,<br>if you can be more specific on What you want to do?<br>Get the simulation results, Create a test bench, Generate a bitsteam file...<br><br>Or just a support in installing the xilinx software.<br><br>Thank you.

Hello @robertferanec  , i have 8 schematics in my project and there is a lot of port in each one , when i create symbol sheet from every sheet   i get very complicate "Top_level"  !  So  have another methode  to do my project . i mean that i don't like to use Herarchical conception ,  can you help me with another methode ?

Have a look at our imx6rex project (you can download altium files from there): <a href="https://www.imx6rex.com/" target="_blank">https://www.imx6rex.com/</a>

Hello , i need some information for the BGA design in altium ! <br>EP4CE30F23C8N  i will use this ship for my card , i need some advices , schematic  ... <br>@robertferanec  <br>please it's so urgent <br>ps ; it's my first design with FPGA

hello , can some one explain to me the regulators circuit please (page 1 )<br><a href="https://www.hdl.co.jp/en/spc/ACM/acm-205/ACM205R1-SCH-C.pdf" target="_blank">https://www.hdl.co.jp/en/spc/ACM/acm...05R1-SCH-C.pdf</a>

@karimoviç start with a reference board. If you do not fully understand the reference board, only do as a few changes as you have to. I would recommend do not change regulators if you are not sure about them.

Thanks for response @robertferanec   , yes i'm starting do this  , but now i don't know how to fix the VCCIO  for each bank of my FPGA , They can work with 1.2 v , 2.5v ,1.8v , 3v and 3.3V  and can't know how to fix the right voltage supply value for each Bank :/  !

It depends what is connected to the specific bank - if a chip what is using 3v3 interface, you need to power that specific bank with 3v3, if you connect there a chip with 1.8V you will need to power the bank with 1.8V, etc

Hi,<br>I designed a board with Artix7 and DDR3 RAM. For connections please see attached. Vivado gave an error and the error screenshot is also uploaded. Do u have any solution for this?

I have not tried DDR3 in FPGA, but I noticed CS in the group - is that correct?

Thank you. You are right about the priorities of pin assignment. I did the pin assignment according to what you showed " using mig generator".

<div class="bbcode_container"><div class="bbcode_quote"><div class="quote_container"><div class="bbcode_quote_container b-icon-fa b-icon-fa--24 fa-solid fa-quote-left"></div><div class="bbcode_postedby">Originally posted by <strong>MustafaE</strong><a href="https://designhelp.fedevel.com/forum/schematic-and-pcb-design/vhdl-and-fpga/12424-ddr3-ram-fpga-connection#post12424" rel="nofollow" title="View Post" class="animate-scroll"><span class="b-icon-fa b-icon-fa--16 fa-solid fa-angles-right" aria-hidden="true"></span></a></div><div class="message">Hi,<br>I designed a board with Artix7 and DDR3 RAM. For connections please see attached. Vivado gave an error and the error screenshot is also uploaded. Do u have any solution for this?</div></div></div></div>Hi<br>I m starting now to study DDR memory interface using FPGA.<br><br>But I hope i can help you...<br><br>It seems your problem is related to PINs assotiation for data/address group signals whitin the bank.<br><br>You should select the correct bank for your device, <b>ONLY </b>using  MIG to select and <b>validate </b>the pins assignment<br>for data and address/control signals.<br><br>Maybe you selected wrong bank (each bank has a different PHY to I/O signals)<br>or you should separate data group in a bank and address/control group in another bank.<br><br>Check it using MIG.<br><br>It could be useful to have a look at a reference schematic, as Robert always says in his lessons <img src="https://designhelp.fedevel.com/core/images/smilies/wink.png" border="0" alt="" title="Wink" smilieid="4" class="inlineimg"> , for banks/groups selection in DDR interfacing:<br><a href="http://https://www.xilinx.com/support/documentation/boards_and_kits/vc709/ug887-vc709-eval-board-v7-fpga.pdf" target="_blank">http://https://www.xilinx.com/suppor...rd-v7-fpga.pdf</a><br>(on page 14)<br><br>and maybe it could be usefull also to check another example of DDR pins assignment, here:<br><a href="https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf" target="_blank">https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf<br><span style="color:#000000">check " design guidelines"</span></a> on page 192 and "DDR3 pinouts Example" on page 213.<br><br>I hope it can help you somehow<br>Regards<br><br>Rocco

Hi everyone<br>I am trying to improve myself as a digital design engineer. First of all I see people who design systems with FPGAs. They generate cores using HDL, add ready to use cores from vendors, use softcore processors and finally come up with a full design. I still couldn't decide where to start. Should I learn VHDL or Verilog syntax; or digital design concepts such as memory usage, clock domain crossing, manipulating data; or wrapping up a total system. Any advice will be appreciated. Moreover if you suggest any resource to follow for a complete tutorial I will be really happy.<br>Thanks

First off all congrats on making the very first post in CHDL and FPGA!!!<br><br>secondly i think if you are really serious about this you should learn both.. because from what i have seen.. most Intel/Altera FPGA users use VHDL and most Xilinx users use Verilog..  but i think these days it doesn't matter much.. but i am not a code writer.. from what i can gather with verilog you have more control options than with VHDL.. <br><br>with regards to your questions about design conecpts. and reading your other post.. I would suggest finding a job in R&amp;D! somewhere you can start at entry level and have people around you that can help you with these questions.<br><br>there are a lot of recources out there. but i think if you want to tinker at home with this.. find a cheap development kit and start doing small things like "hello world" projects.. meaning a blinkig led.. reading out an IO.. and progressing from there.. <br><br>it might help telling us a bit more from your background / age / experiences so far ..or where you are located in the world<br><br>

I agree with @Paul van Avesaath.<br><br>PS: Jordan Christman has many courses about FPGA on Udemy: <a href="https://www.udemy.com/user/jordanchristman/" target="_blank">https://www.udemy.com/user/jordanchristman/</a>

Thank you both @robertferanec  and @Paul van Avesaath !! I already have a job in R &amp; D and my job description started changing due to the projects in my company. I posted the question for this. I tried starting from beginning such as hello world and led blinking projects; but those look very simple. I mean if there is a book or video series which teaches how to implement design blocks and finish a project, that will give me really good inspiration. Maybe such course will pay off and you want to do that @robertferanec ?

the trick with VHDLand  Verliog is that it is parallel thinking.. every clock cycle there is something happening.. yes you can create a state machine and go serial again.. but really getting the grasp of parrallel thinking is pretty hard.. just google  around for tutorials.. also start thinking about projects for your self.. what do you think you can make.. and how would you make it..<br><br>you have to start at the beginning even it looks very simple.. but if you start at something too hard you will loose your energie too.. <br>I dont know what company you work, but maybe you can spend one day a week with one of your senior collegues.. and see what you can learn from them..<br>there are plenty of books out there. also if you call a local FPGA vendor/supplier the will have  courses aviable form time to time.. <br><br>were are you from? there are loads of courses but maybe not near you...<br>

I am from Turkey, I found lots of tutorials and courses. But I want to learn is as follows.<br>What is BRAM and how do I use in FPGA; when should I use external RAM; what are the cons and pros of each; what is AXI streams and when to use it; when should I add a softcore processor to the system; what should I do if I want to export data via ethernet, USB or PCIExpress. At the beginning I want to learn these concepts.

ah now i get it, your trying to find an education. something like  a course. well ask you local vendors (find out who is supplying components to your company, ask them if they know or maybe host local events) I ussually get spammed with stuff like online course, come and visit the expo stuff like that..there are a lot of talks during expo's and you meet a lot of people in the industry.. ask on linked in if someone can suggest a good VHDL/VERILOG course.. but try and do it locally.. maybe there is a university or school that provides extra classes for external people..

B-RAM (Block ram) <a href="https://www.youtube.com/watch?v=fqUuvwl4QJA" target="_blank">https://www.youtube.com/watch?v=fqUuvwl4QJA</a><br><div class="b-bbcode b-bbcode__url b-bbcode__url--preview"><a href="https://www.nandland.com/articles/block-ram-in-fpga.html" target="_blank" rel="nofollow" class="urlimg_container"><img class="js-img-fallback" src="https://nandland.com/articles/images/block-ram-cyclone-v-intel.png"></a><div class="urlinfo"><div class="title ellipsis"><a href="https://www.nandland.com/articles/block-ram-in-fpga.html" target="_blank">Lesson 15: What is a Block RAM (BRAM)?</a></div><div class="url ellipsis"><a href="https://www.nandland.com/articles/block-ram-in-fpga.html" target="_blank">https://www.nandland.com/articles/block-ram-in-fpga.html</a></div><div class="meta">What is a Block RAM (BRAM) in an FPGA? Tutorial for beginnersThey're used for FIFOs, Dual Port Memories, and More!Block RAMs (or BRAM) stands for Block Random Access Memory. Block RAMs are used for storing large amounts of data inside of your FPGA. They one of four commonly identified components on an FPGA datasheet. The</div></div></div><br><br><a href="https://www.youtube.com/watch?v=fqUuvwl4QJA" target="_blank">A</a>xi stream <a href="https://www.youtube.com/results?search_query=axi+stream+interface" target="_blank">https://www.youtube.com/results?search_query=axi+stream+interface<br><br>t</a>here are tons and tons of information on the web and on youtube (sorry to spam other channels @robertferanec )<br><br>i can understand where you are comming from (wanting to know this), but these questions are not something that is easy to explain because 99% is project dependend and are very advanced concepts to implement.. <br>

<div class="bbcode_container"><div class="bbcode_quote"><div class="quote_container"><div class="bbcode_quote_container b-icon-fa b-icon-fa--24 fa-solid fa-quote-left"></div>Maybe such course will pay off and you want to do that robertferanec ?</div></div></div>- I would love to, do not have time <br> <br><br><br>Source: <a href="https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&amp;CategoryNo=205&amp;No=1046&amp;PartNo=2" target="_blank">https://www.terasic.com.tw/cgi-bin/p...=1046&amp;PartNo=2</a>

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