Routage

[karimoviç]

hello , can someone explain to me what's the meaninge of "routing signals with FPGA" with multiplexrs for exemple.

[Paul van Avesaath]

i think it meand using an FPGA as a MUX. so you have input signals on it and output signals on it, lets say 8x8 then you have the possebility to create any input/output path connection.

[chitransh92]

Hi karimoviç ,
FPGA as a device is different than Microprocessor or Microcontrollers.

Essentially it is a blank white board and you can create any logic that you want inside and FPGA.
"Routing signals with FPGA" without the context can have various meaning out of which one is highlighted by Paul van Avesaath

But in FPGA when ever you design a logic you actually route a signal physically like all the parameters that are associated with a physical copper trace apply to the FPGA routing and all the signal delays must be accounted for...
So "Routing" in FPGA means Routing in its literal sense..

Thank you.

[robertferanec]

For "routing signals through FPGA", I would rather recommend to use a CPLD (FPGA usually has to be loaded after start, CPLD is programmed and then works). This technique is usually used for something where you would otherwise need many Gates or Logic chips to get the behavior you need (and very often it is used to generate chipselect). Also, if you use CPLD (instead of doing it through chips and routing) you can re-program the behavior - eg. in case you make a mistake, you can change it (that would be hard if you would chips and route it on PCB - you would need a new board version, with CPLD you just update the firmware).

[gyuunyuu1989]

The OP needs to provide more details. Routing within FPGA is the process by which the logic resource (mainly logic gates and flip flops) are physically connected together using the routing resource. This makes it possible for electrical signals to travel between the logic components that implement all the combinatorial and sequential functonality of the design. The routing process is carried out automatically during the floorplan stage of design compliation, this step follows the design synthesis stage where the design usually described in an RTL description in HDL is converted into a netlist.