Errors doing PCB design during design rule check

[Ivan_Mendez]

I´m doing fedevel course of electronic design named Altium Essentials. I have just finishing lesson 4 but I can´t continue with lesson 5 because when I did design rule check at the end of the lesson 4, then appeared to me 59 errors Wich I don´t know how to fix them.

I attach a screen capture. What can I do to solve this situation an continue with lesson 5?

[Ivan_Mendez]

I fixed the errors by coorecting via hole from 0.6 mm to 0.3 mm. I think it happends because even I have defined rules on Vias definition when I selected via its diametre width was 0.6 mm and its hole was 0.6 mm instead of 0.3 mm. how can I set the vias dimension to work with them properly? I refer that I don´t want to define each via dimension each time that I selected one of them. Thanks.

[qdrives]

Have a look at via templates https://www.google.com/search?q=altium+via+template