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I have also been quite confused about “courtyard” vs. “overlay” and their role in component placement. Most of the comments in this thread have been from 2016, before I started using Altium, so I’m not sure what may have changed. Altium has a component clearance DRC rule, which is used to flag errors if components are placed too close to each other. I do not have the IPC7351, but here are my conclusions after watching a couple of videos from Altium.
courtyard video: https://www.youtube.com/watch?v=Qhe8BgAFokc
courtyard summary: The courtyard outline is supposed to extend beyond the worst case boundary of the component, including any pads. How far beyond is a function of the footprint density level (maximum=0.5mm, median=0.25mm, minimum=0.1mm).
silkscreen overlay video: https://www.youtube.com/watch?v=ILX1ruslczc
silkscreen overlay summary: The overlay outline is supposed to follow the outline of the component body and be visible when the component is placed on the board. It should only follow the outline of the body of the part and not the pads. This is somewhat limiting for small discrete chips, as the overlay cannot overlap onto the pads. Footprints for small devices like 0402 or 0201 will not have any overlay outline at all.
Here is how I believe that Altium (AD20) determines if there is a violation of the “component clearance” requirement in the DRC rules:
courtyard video: https://www.youtube.com/watch?v=Qhe8BgAFokc
courtyard summary: The courtyard outline is supposed to extend beyond the worst case boundary of the component, including any pads. How far beyond is a function of the footprint density level (maximum=0.5mm, median=0.25mm, minimum=0.1mm).
silkscreen overlay video: https://www.youtube.com/watch?v=ILX1ruslczc
silkscreen overlay summary: The overlay outline is supposed to follow the outline of the component body and be visible when the component is placed on the board. It should only follow the outline of the body of the part and not the pads. This is somewhat limiting for small discrete chips, as the overlay cannot overlap onto the pads. Footprints for small devices like 0402 or 0201 will not have any overlay outline at all.
Here is how I believe that Altium (AD20) determines if there is a violation of the “component clearance” requirement in the DRC rules:
- If there is a 3D model for the component(s) it uses the edges of the 3D model.
- If there is no 3D model, but there is a courtyard outline, it uses the courtyard outlines.
- If there is no 3D model and no courtyard outlines, it estimates the size of the components, but it never appears to use the overlay outline.
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