Top Overlay vs. Courtyard

[milos.stankovic]

In order to place components as it is shown on "Correct" picture option Preferences->Interactive Routing->Component pushing must be set as Ignore. If it is set to Avoid, Altium will take either Component Courtyard or Top Overlay, whichever is bigger for calculating horizontal Component Clearance. Even if you define Component Courtyard Layer and its Layer Pair as Courtyard, Altium behaves the same. It may be some bug.

[Tom Yunghans]

I have also been quite confused about “courtyard” vs. “overlay” and their role in component placement. Most of the comments in this thread have been from 2016, before I started using Altium, so I’m not sure what may have changed. Altium has a component clearance DRC rule, which is used to flag errors if components are placed too close to each other. I do not have the IPC7351, but here are my conclusions after watching a couple of videos from Altium.

courtyard video: https://www.youtube.com/watch?v=Qhe8BgAFokc
courtyard summary: The courtyard outline is supposed to extend beyond the worst case boundary of the component, including any pads. How far beyond is a function of the footprint density level (maximum=0.5mm, median=0.25mm, minimum=0.1mm).

silkscreen overlay video: https://www.youtube.com/watch?v=ILX1ruslczc
silkscreen overlay summary: The overlay outline is supposed to follow the outline of the component body and be visible when the component is placed on the board. It should only follow the outline of the body of the part and not the pads. This is somewhat limiting for small discrete chips, as the overlay cannot overlap onto the pads. Footprints for small devices like 0402 or 0201 will not have any overlay outline at all.

Here is how I believe that Altium (AD20) determines if there is a violation of the “component clearance” requirement in the DRC rules:

1. If there is a 3D model for the component(s) it uses the edges of the 3D model.
2. If there is no 3D model, but there is a courtyard outline, it uses the courtyard outlines.
3. If there is no 3D model and no courtyard outlines, it estimates the size of the components, but it never appears to use the overlay outline.

It seems like many designers are making their silkscreen outlines surround the entire component instead of just the component body, and then using that silkscreen outline as the guideline for component placement instead of using the courtyard outline. Maybe this is more of a legacy approach? Is the courtyard a newer concept?

[EVW13]

if i understand L version is for high density placement so i my case under the GBA. If i use L version I hope i will have no problem with the assembly . I will not assembled by hand i will send the board to a company specialized in assembly. do you think it will be ok?

If you do nice courtyard and do placement without overlapping there will be no problem at all.

I tried the component wizard in circuitmaker for a cap0402. you can see the result in the picture:
[ATTACH=CONFIG]n3420[/ATTACH]

i see there is a difference in the solder mask layer compared to the capa in the community:

In terms of PLE output(copper/geometry) all they looks wrong, however upper one looks more realistic compared to lower. I've noticed that wizard from Altium/Circuitmaker tries to arrange pads mostly under package for L, which is strange. And meaning soldermask openings for 0402: 0.05mm is good start, less is better, more isn't acceptable- on your pic opening is greatly oversized.

I have also question about capa0402 from the community. For the L and N version, the 3D model seems to be larger than the pad in the L version. Is it normal? See the picture below:
L version:
[ATTACH=CONFIG]n3423[/ATTACH]
N version:
[ATTACH=CONFIG]n3424[/ATTACH]

If 3D models are really different that is serious mistake.

[ljo]

I have also question about capa0402 from the community. For the L and N version, the 3D model seems to be larger than the pad in the L version. Is it normal? See the picture below:
L version:

N version:

[ljo]

[QUOTE=EVW13;n3411]Hi ljo, please review my comments below:

2) According to you your pic I strongly believe than L density will serve the best. However those footprints don't look like IPC-7351 compliant: subject was covered few posts earlier.

if i understand L version is for high density placement so i my case under the GBA. If i use L version I hope i will have no problem with the assembly . I will not assembled by hand i will send the board to a company specialized in assembly. do you think it will be ok?

4) I don't understand, can you explain?

I tried the component wizard in circuitmaker for a cap0402. you can see the result in the picture:


i see there is a difference in the solder mask layer compared to the capa in the community:



it is normal? what is the right way?

[EVW13]

Hi ljo, please review my comments below:

1) N-Nominal, M-Most, L-Least, all these are pattern density definitions covered by IPC-7351. You said you downloaded PLE- you can check them in tab “Terminal->Density level”.

2) According to you your pic I strongly believe than L density will serve the best. However those footprints don't look like IPC-7351 compliant: subject was covered few posts earlier.

3) Yes, all those 0402 footprints are kind of “Circuitmaker understanding of IPC-7351”- once again, you can run your own calculations via PLE and then compare and see differences (they do exist). What about overlapping- while you're still doing correct placement density level doesn't matter, courtyards shouldn't be overlapped(except edges) under any circumstances. Also, just to repeat myself: courtyard edge-to-edge placement is gridless in general and only can be achieved by geometrical transformations.

4) I don't understand, can you explain?

5) See p.1, just run your PLE and compare results.

P.S. If it's your first project I strongly recommend you to start from SMPS layout: there is no challenge in routing DDRx memories when you do understand design guidelines, however polygonal layout(Power and Ground + Switching nodes) is exactly kind of thing where 95% of PCB designer fail. Particularly it looks most weird in designs made with Allegro: all high-speed stuff is made really nice, and the rest including polygonal layout is just a crap. It will be also really good to learn how to do footprints for parts like on pics below(my own 3D models are attached), of course with overriding manufacturer's recommended land pattern.

[ljo]

thanks for all these information.

1) But I dont understand what does it means "N, M or L pattern density according to IPC-7351"?

2) In which case am I? I am designing a simple board (soc ti am3358 + sd card + ddr3) just to make my first PCB and learn. The pitch of the soc is 0.8mm. I placed all the 0402 decoupling capacitors under the SOC.



3) I took a 0402 cap 10nF from the circuitmaker community. But I dont really understand, there are three versions of the footprint. I suppose a N, M and L version. And which one can i use to be able to place my capa correctly without overlapping each others?



4) And for all the footprints, there is something strange for the soldermask it seems that there is only one soldermask and not two. Is it correct?



5) Last question, how to be sure that these footprint are IPC-7351 compliant? I downloaded PLE free version. Can I compare metrics of the footprint with footprint generated by PLE? Or maybe is it better to regenerate the footprint with the component wizard? For info i use CircuitMaker so I think i cant generate footprint for it. Maybe im wrong?

[mairomaster]

Hi guys,

If you mean duplicating courtyard geometry also on silkscreen layer that generally is only possible when you use N and M pattern density according to IPC-7351, while in case of L you most probably will not be able to make such contour without violating “Silk-to-Copper distance”-like rules.

[ATTACH=CONFIG]n3401[/ATTACH] [ATTACH=CONFIG]n3402[/ATTACH]

I meant I keep the two layers completely independent - each of them serves its own purpose. The courtyard is used for placement information/guidance as you explained and the silk screen is used purely for user information.

I agree that if only silk screen is used for courtyard purposes, you can't really have small L components, since you will not be able to meet the silk screen clearance (don't have time now to double check that).

With small resistors and capacitors I don't have silk screen at all. With some big component (ICs for example) the silk screen shows the body outline, while the courtyard is sort of an extended version of the body outline.

[EVW13]

Hi guys,

Let me add few comments regarding mentioned subjects:

Altium doesn't support courtyard directly

Yes, and this is significant fault of Altium- it does recognize courtyard as the entire footprint, means it allows overlap when rules covering gap between components are set to 0. You can compare it with Allegro, where “Placement Boundary” layer is courtyard layer- take a look at pic from attachment: if one try to overlap those boundaries that will give an error, however courtyard edge overlaps are allowed- which is correct and logical obviously. So Altium sucks here

Assembly houses don't normally need the courtyard information for the assembly process - the courtyard just helps you to create a design which could be assembled without problems.

Correct, it's not required for assembly completely, you only need it at design stage.

I personally prefer using a separate layer for the courtyard as it gives me more flexibility and the ability to do whatever I want with the silk screen. I also use the courtyard layer for assembly drawings.

If you mean duplicating courtyard geometry also on silkscreen layer that generally is only possible when you use N and M pattern density according to IPC-7351, while in case of L you most probably will not be able to make such contour without violating “Silk-to-Copper distance”-like rules.

Now it is clear.

Meaning the exact requirement in courtyard definition: biggest benefit of it is possibility to achieve most dense placement while still remaining with IPC-7351, but it's obvious fact that far not all boards require that kind of placement. I'll tell you more, lot and lot of board are physically just oversized(artificially) to perform fast and easy component placement using grid- it's standard and mainstream approach, but it doesn't work in true high density designs. At the same time, placing components courtyard edge-to-edge in 90% of cases will lead you to high-end HDI designs area, but it's not main case: such placement isn't based on grid but on geometrical transformations thus being most complicated and time consuming method- however bringing the most high quality result by all means. If one doesn't have experience in such placement it's very easy to mess with your project in such way that will definitely turn into deep relayout/redesign

[ljo]

Thanks a lot for these precious information.

I was just a bit confuse because in the robert feranec 's courses he didnt mention courtyard. Now it is clear.

[mairomaster]

I will try to summarise:

The courtyard is mainly used to ensure proper physical spacing between the components. If you don't have enough space between them, you risk to have problems during the assembly process, due to imperfections of the pick and place machine and variance of components' actual size. For electrical spacing different rules are used (e.g. copper to copper, minimum solder mask sliver, etc).

Assembly houses don't normally need the courtyard information for the assembly process - the courtyard just helps you to create a design which could be assembled without problems.

I personally prefer using a separate layer for the courtyard as it gives me more flexibility and the ability to do whatever I want with the silk screen. I also use the courtyard layer for assembly drawings.

[ljo]

Do you mean for checking if components fits i have to print the assembly and buying the components and puts all of them on the assembly drawing paper?
For the assembly it seems that the courtyard is not mandatory, am i right? When the courtyard is necessary, isnt it for placement only? And in your course you use top overlay as courtyard, right?

[robertferanec]

Yes, we use F and G, but when you are creating new components you may want to check if it fits there. Especially capacitors or beads may have different size occasionally.

Altium doesn't support courtyard directly, that is why I do no really use it and we only use the overlay layer instead. In Altium, I normally use 3D models to check if everything fits ok. In the previous company, where I used to work, they used Allegro and they always created courtyard.

[ljo]

In our designs, we usually draw the Top overlay as the biggest size of the component - so you are sure if you place two components close to each other with touching Overlay, it will be possible to fit them. In assembly layer, we draw a simple shape around the component, but we do not use this layer as the component courtyard - it's just to show component location.

How do you get the maxsize of the component for example for a smt capa? I learned from your course that you use this pdf (https://www.ibselectronics.com/pdf/p.../smt_notes.pdf) for the footprint. Do you use the F and G value in the table to define the top overlay line?

For my project I use CircuitMaker and I dont know if i have to trust the footprint done by someone else. It seems that anyway I have to draw at least silkscreens for the assembly drawings. And for some components for example they use courtyard layer. I didnt kwnow what it is. It is confused for me. Is this layer is mandatory for the assembly and also layout (placement)? can we just do as specified by Robert Feranec in his course(top overlay for placement)?

[EVW13]

zeino, at least you can try PLE light and see what values it puts in final footprint- and/or run trial to get full library during the trial time: it's enough to build entire EIA packages family at the very least. What about IPC-7351 standard, it's worth to mention that in case of purchasing PLE you'll get free copy of it- but I want to cover this in context of mairomaster's words about non-ideal results under some circumstances: me, I always develop 3D for footprint because 3D checks footprint and vice versa, and some time it's clear that for example manufacturer's footprint is wrong, or calculated one isn't good enough- meaning PLE, I had some non-ideal footprints with side concave package, footprint pads didn't cover physical pads properly.

What abour3D modeling itself- like it was said, there is no such software that covers all package nuances even for standard parts, so building stuff by your own is really great way as you gain control of the situation. Of course it's possible to search some free stuff on sites with 3D models, but my opinion it's not really good approach- there are a lot of authors which have their own very specific understanding of what is right and what is wrong, there are bunch of different methodologies and placing all such parts made different way makes you PCB look like mess. And I should say that control level is so high that you can even make parts which have bad or missing drawings in datasheet- here is example: BK-18650-PC4- incomplete drawings(for making 3D) and dummy original model(plain box).