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Top Overlay vs. Courtyard

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  • Top Overlay vs. Courtyard

    Is Top overlay layer (Yellow Line) same as courtyard space of the component? It seems they are different. How would we know how close the components can be to each other specially with SO8's or the ISIL chip. We don't show with the mask the necessary distance clearance to chip anywhere do we?

  • #2
    In our designs, we usually draw the Top overlay as the biggest size of the component - so you are sure if you place two components close to each other with touching Overlay, it will be possible to fit them. In assembly layer, we draw a simple shape around the component, but we do not use this layer as the component courtyard - it's just to show component location.


    • #3
      Hi zeino,

      Component courtyard is completely not equal to silkscreen outline- generally silkscreen is atavism from 70x years when PCBs were manual assembly was the mainstream. If you take a look at any modern PCB, specially HDI with tight placement you will see there is no any silkscreen outline and no polarity marks- because it's not required for any modern automated assembly.

      At the same time tight courtyard is extremely important footprint detail as it defines the minimum distance between components- least distance is courtyard edge to edge.
      Last edited by EVW13; 02-16-2016, 07:53 PM.


      • #4
        Overall I agree with EVW13's opinion. However, I think that some silk screen information can be quite useful during debugging of a board. That would most often be reference designators (usually only with bigger components due to the lack of space for all of them), test point labels and other useful visual information.

        It is true that the idea of the courtyard is to allow the densest placement of components without problems during the assembly. I depends on the software you are using though, if you will be able to use the courtyard properly. Altium Designer for example doesn't have a default rule which accounts for courtyard clearance. I haven't found an easy way to set one up as well. And without a rule, you can use the courtyard for visual inspection and assembly information only. It is a different story of course that Altium has a different mechanism of checking components clearance, but this goes into an off-topic.


        • #5
          Yes, in some cases silkscreen may serve good job for better visual recognition- but far in not all cases it can be implemented, and what is more important- needed to be implemented: if one has for example testbench with pogo pins and other stuff if it's not required, if one is soldering wires to each TP thinking like”Hmmm, and what was that TP?” of course it's better to have some board level info.

          What about courtyard and it's implementation in Altium- I can say that in tight designs best way to use all benefits of courtyards is to switch clearance rule(component to components) to “0” and then place components using geometrical relations- in Altium there is very nice mechanical snaps mechanism which is almost the same as in MCAD. That is even more beneficial specially assuming that it's not possible to make such rule that covers placement like on picture from attachment(proportional courtyards) and you're dealing with cases like in this topic. Click image for larger version

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          • #6
            Thank you guys for your insight on this. I think in the Video and the way footprint is being made there is a mixture which is not 100% logical. At one hand on the overlay we abide by the IPC rules of courtyard in depicting the overlay for chip cap and resistors and the other hand we don't do that for the IC's so there isn't the consistency on what we are trying to do and that raises the question asked here: "What is the overlay for?" I agree with what you say about overlay on previous posts ("EVW13, Mairomaster") . It is just an indicator for the component and that is it. On the other hand courtyard and manufacturing courtyard (as you said) are assembly indicators and are of mechanical nature and has to be treated that way in my opinion.

            In footprint we don't need to shape the courtyard on the overlay (we may even go with component outline+pads) but if we want to abide by the IPC rules in our design we need to define a courtyard and component outline as Altium suggests in our footprints as extra layers. I believe Altium IPC compliant footprint generator does that but I still have to learn it.

            Based on what I saw so far from Altium, if in our footprints we do have different layers for courtyard and component outline we should be able to put rules for them on the placing and that would fulfill the purpose of courtyard but that is so much extra work for building the footprint for that purpose by hand. I think that is why they built the IPC compliant tool. FP wizard puts courtyard on layer 15 and outline on layer 13. Logically for each layer one should be able to define rules accordingly.

            Still if making the footprint myself I will restrict the overlay to component outline+pads (like what EVW13 has in his picture). Based on IPC standard one can add constant value to (component outline+pads) to make sure it abides by one of 3 levels of IPC clearances, if one doesn't have the courtyard defined in its footprint layers. That means, the overlay will be around the nominal pad positions and then I would put rule on it for the courtyard access of 0.25mm. I think it should be possible to tell Altium to abide by that clearance values form the (component outline +pads) but I still have to learn how. From IPC stand point the pads position and size differ on what class you are using but if I follow that rule without the IPC footprint all footprints I build without the FP wizard would be consistent with the nominal value.

            I think EVW13 on his last post is showing the same concept but I didn't understand the 0 clearance thing. It seems based on your experience putting rules on the layers when placing is not as easy as I think it should be. I need to experience that and learn more about it.


            • #7
              Meaning Altium I can say with confidence that its footprint calculator has nothing with IPC-7351 standard: as maximum it looks like it has some own “understanding” of it with pretty specific values as result. On attached pic you can see difference between Altium calculator and true- IPC compliant one:

              Click image for larger version

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              What about assembly issues- most probably you saw pic like that in many PCB designs:

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              Which shows how often people underestimate the value of nice courtyards- because the right case is below.

              This particular issue is coexisting very often with its “best friends”- mix of different land patterns(least, nominal, most) and badly though-out copied footprints from really wired libraries. Resuming all above- better not believe to anyone and always do own libraries.

              What about courtyard definition- you can select any mechanical layer for it, and in library it's only required to define it on single layer. In target design you should use mechanical pairs then- and meaning “zero clearance rule from previous post” it's possible to rephrase it like this: courtyard line has width which matters, so imagine you want to place couple resistors like on pic above- to perform you use that rule, switch on mechanical snaps on mech layers, select footprint's vertex in courtyard area and just move to other vertex and thus place parts edge-to-edge.


              • milos.stankovic
                milos.stankovic commented
                Editing a comment
                In order to place components as it is shown on "Correct" picture option Preferences->Interactive Routing->Component pushing must be set as Ignore. If it is set to Avoid, Altium will take either Component Courtyard or Top Overlay, whichever is bigger for calculating horizontal Component Clearance. Even if you define Component Courtyard Layer and its Layer Pair as Courtyard, Altium behaves the same. It may be some bug.

            • #8
              EVW13 very nice pictures!

              Meaning Altium I can say with confidence that its footprint calculator has nothing with IPC-7351 standard: as maximum it looks like it has some own “understanding” of it with pretty specific values as result. On attached pic you can see difference between Altium calculator and true- IPC compliant one
              What IPC calculator do you use / recommend?


              • #9
                This one. But only calculator, without .STEP output- there is no such footprint making software that covers all package nuances or do packages like below- me, I design all 3D stuff by myself.

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                • #10
                  EVW13 Thanks. I heard also some other people to say, that it is very useful and worth the money. But I have not tried it.

                  What do you use for 3D? The models look fantastic!


                  • #11
                    PLE is worth of trying as it greatly simplifies footprint creation according to IPC-7351 and in most of cases result doesn't require post-editing. Take a look also at this one- but keep in mind, this one is a different story and generally can't replace PLE(I tried both)- my opinion, the only real advantage of it is making schematic symbols from PDF.

                    For 3D modeling I use Solidworks- after all test-drives I realized that for me it's best software as my personal preference is nice and intuitive interface and thus, lack of “fighting with software” in the end of the day. Making 3D stuff in it is extremely easy and logical -also, I use it for color restoration for those models supplied by manufacturer: pretty often they have omitted colors, and it's reasonable to at least identify conductive elements and surfaces for better visual recognition and control- as the example you can see that USB footprint in this thread, as the attached footprint contains model with restored colors. And of course it helps a lot to make and check footprints- specially if you're not using EDA with nice mechanical snaps, good example is Allegro: imagine that you need footprint like below- making it in allegro “straight” way is just a waste of time, but with using MCAD it's really simple.

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                    ​ Here is other example of custom 3D model and custom footprint for very commonly used package- TDSON-8(also done in allegro)

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                    • #12
                      EVW13 Thank you very much. Very useful tips and links.


                      • #13
                        I have worked both with Altium IPC wizard and PCB Library Expert. I also have access to the official IPC-7351B standard. I also think that PLE is made very well and it is quite professional - I have checked its calculations and compared them to the IPC standard and it seem pretty accurate. I have achieved good results with Altium IPC wizard as well, but I agree that it is not quite as powerful and it does some magic behind the scenes which is not very clear to the user.

                        To achieved good results, the user need to have good understanding of the IPC standard with either of the tools. It is very important to enter all settings right (and there are many of them) in order to achieve a proper footprint. Also the user needs to have a detailed information from the manufacturer about the particular part in terms of sizes, tolerances, etc.

                        I was a bit surprised by the difference in the footprints of 0805 capacitors demonstrated by EVW13. I repeated the experiment using Altium 16 and PLE 2012. I used exactly the same input settings for both programs. Here is the result:

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                        The dimensions of the pads and the courtyard are exactly the same, with one exception. Altium uses less space between the pads, which accounts for bigger variations of the capacitor's contacts inner spacing. I spent quite some time figuring out how exactly Altium does this calculation and realized it uses a formula slightly different than the IPC standard (but only for the pad spacing - everything else is the same). This approach seems to be the more reliable one, since in practice there is a slight chance that the capacitor contacts will be spaced closer than the IPC way of calculating it. However, that could lead to other problems as well, like having not enough solder mask between the pads which may lead to shorts in some cases.

                        If you are interested I can explain more about the different ways of calculating this particular dimension (and others maybe) but the mathematics is reasonably involved and somehow boring.

                        I am assuming EVW13 didn't use exactly the same input settings for the 2 footprints, hence the bigger difference.


                        • #14

                          In fact it's far not the first time I recognize such difference between FP and PLE- but I should advise you to test your settings in modern PLE version(2015.21): you will get exactly the same results as me. I use 2015.20 and generally it provides significantly different results compared to FP- and those result correlate with reality really nice, never ever I received issues report covering PCB assembly.

                          It's also worth to note that modern PLE calculates footprints according to IPC-7351C.


                          • #15
                            Yep, that could be the reason for the differences as well I have the feeling though, that Altium still uses IPC-7351B (maybe I read it on the Altium forum at some point as well). That would also explain the difference with the new PLE.