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Is it wrong to join the grounds in a polygon like the picture below. Same goes on the ground pins on the ISL 6236 which are adjacent. I can think of it having extra capacitance between the ground layers linked by a via which is inductor and forming a resonant circuit in high speed but other than that in low speed I don't see any problem. May be it is also bad for solder paste and reflow. What is your opinion about it?
Added after the Question: I see at minute 20:18 of the video for the chip GND pin the data sheet says connect to the GND of the chip and done individually each pin to the pad. Now if we make a polygon and connect both to the pad would we be breaking a rule? It would be a less resistive GND connection. Just curious why we don't do that other than reflow reason or being ugly.
Added after the Question: I see at minute 20:18 of the video for the chip GND pin the data sheet says connect to the GND of the chip and done individually each pin to the pad. Now if we make a polygon and connect both to the pad would we be breaking a rule? It would be a less resistive GND connection. Just curious why we don't do that other than reflow reason or being ugly.
If you have any other questions, let me know.
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