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When to use uVIA and POLYGON?

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  • When to use uVIA and POLYGON?

    I took a screenshot of my project. My question is :
    when we have multiple GND pin as the screenshot , is better to connect each GND pins to the GND plane with a uVIA or instead use polygon to connect all these pins together and after connect the polygon to the ground plane with a uVIA?

    Click image for larger version

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  • #2
    What is done is the most cases and seems optimal is to connect each ground via separately to the internal ground plane/polygon with a micro via. Apart from the biggest advantage that you have the smallest possible inductance connection to ground this way, if you are using vias in pads, you also have space to put tracks between the pads on the top layer.

    There is no real advantage to use a polygon on the top layer to connect the vias together, since you will still need to additionally connect each via to the ground below with a separate micro via for a smaller inductance connection.

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    • #3
      1) I never use uVIAs for GND or Powers. I always use through hole VIAs (many times uVIA current limits are much lower than current limits for through hole VIAs)
      2) If possible, I use one through hole VIA per power pin (if not possible, I connect maximum two power pads through one through hole VIA)
      3) If power pins are located in same area, by the end of design I will draw a polygon on the layer where component is placed (I have seen this used in some Intel motherboard layouts). Even if I use a polygon, I still keep the rule from point 2 (one VIA per one power pin or maximum two power pins per one VIA) - so basically I will have one polygon with multiple VIAs

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      • robertferanec
        robertferanec commented
        Editing a comment
        Usually even for small pitch there should be option to place through hole VIAs - they keep there some space or you place vias between the pads with same net (e.g. GND) so there is no clearance violation. But I try to avoid using extremely small pitch components, so I may be wrong and there may be some with no other options just uVIAs.

      • mairomaster
        mairomaster commented
        Editing a comment
        On one of our boards we have a 0.5 mm SoC for example and we can't use through hole vias there. However, we are trying to use mechanical blind vias to connect the stack in the inner layers where possible. Those are extreme cases though. Apart from that I agree with you.

      • robertferanec
        robertferanec commented
        Editing a comment
        That must be really tough design.

    • #4
      Originally posted by robertferanec View Post
      1) I never use uVIAs for GND or Powers. I always use through hole VIAs (many times uVIA current limits are much lower than current limits for through hole VIAs)
      2) If possible, I use one through hole VIA per power pin (if not possible, I connect maximum two power pads through one through hole VIA)
      3) If power pins are located in same area, by the end of design I will draw a polygon on the layer where component is placed (I have seen this used in some Intel motherboard layouts). Even if I use a polygon, I still keep the rule from point 2 (one VIA per one power pin or maximum two power pins per one VIA) - so basically I will have one polygon with multiple VIAs

      Yes it's quite difficult and normally you can do things only one way - the right way, otherwise it is not working due to the lack of space.

      EDIT: I wanted to put the comment above, but didn't quite work.

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      • #5
        Originally posted by robertferanec View Post
        1) I never use uVIAs for GND or Powers. I always use through hole VIAs (many times uVIA current limits are much lower than current limits for through hole VIAs)
        2) If possible, I use one through hole VIA per power pin (if not possible, I connect maximum two power pads through one through hole VIA)
        3) If power pins are located in same area, by the end of design I will draw a polygon on the layer where component is placed (I have seen this used in some Intel motherboard layouts). Even if I use a polygon, I still keep the rule from point 2 (one VIA per one power pin or maximum two power pins per one VIA) - so basically I will have one polygon with multiple VIAs
        Thank you i will follow these rules.

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