decoupling capacitor placement?

[ljo]

hello,

I want to ask if anyone can point me to an article or a document or website where I can have information on how to know placing decoupling capacitor. In the AM3358 datasheet, they just specify types of decoupling cap and how many but they dont help on where to place to still be effecient? I always see place the decoupling cap as close to the pin. But how can I know if i put any capa at any place if it s still effecient? How can i calculate the max distance to the power/GND pins?

[robertferanec]

This is from iMX6 Design guide (it is always very similar, just the recommended number of capacitors and the capacitance may be different):

Placing decoupling capacitors

The fanout scheme creates a four quadrant structure that facilitates the placement of decoupling bulk capacitors on the bottom side of the PCB.

The 0201 decoupling and 0603 bulk capacitors should be mounted as close as possible to the power vias. The distance should be less than 50 mils. Additional bulk capacitors can be placed near the edge of the BGA via array. Placing the decoupling capacitors close to the power balls is critical to minimize inductance and ensure high-speed transient current demand by the processor.

A correct via size is critical for preserving adequate routing space. The recommended geometry for the via pads is: pad size 18 mils and drill 8 mils.

The following list provides the main recommendations for choosing the correct decoupling scheme for the i.MX6 family boards.

• Place the largest capacitance in the smallest package that budget and manufacturing can support.
• For high speed bypassing, select the required capacitance with the smallest package (for example, 0.22 μF and package 0201).
• Minimize trace length (inductance) to small caps.
• Series inductance cancels out capacitance.
• Tie caps to GND plane directly with a via.
• Place capacitors close to the power contact of the associate package designed from the schematic.

The i.MX6 SABRE SD (Smart Devices) CPU uses the preferred BGA power decoupling design. Note that the layout is available through www.freescale.com. Customers should use the reference design strategy for power and decoupling.

I believe, you can simulate the stuff (I have never done that). It can take you a lot of time. I usually trust the reference design and just do it as recommended by the chip manufacturer.

ljo if you find some good documents, please share them. I will be very happy to read them.

[ljo]

Thank you.
I found these websites:

http://www.eetimes.com/author.asp?section_id=36&doc_id=1320354

http://www.eetimes.com/author.asp?doc_id=1320429

[ljo]

It is interesting because you can really calculate the max distance where you can put the decoupling capa.
For example in my project i use the soc am3358 from ti. I calculated the target impedance because i have access to the max voltage ripple and max current of each power pins in the datasheet. But i dont know the max frequency of the current variation on each pin so i dont know until which frequency the impedance should be under the target impedance. This info is not in the datasheet.
Have you already heard about this?

[robertferanec]

Once, we had a board smoothly passing all the simulations and failing in the real world. Since then, I do not blindly trust numbers / calculations / simulations. There are many factors what can not be simulated or may be forgotten to be added or included.

Therefore, I always try to do everything the best - so I try to place the capacitors as close as possible even it could possibly work when they are placed further

[ljo]

Thank you for the answer.
When i look in the reference design from ti, i see some decoupling caps which are not necessary place under the bga but a little bit far and in the datasheet they say place the decoupling cap close the power pins. That s why i want to understand the method and calculation where i can place caps.
I will follow your rule and do my best to place decoupling caps as close as possible to the power pins.