Hello All,
I'm wondering if anyone could help me.
Recently I came across the topic package length in some articles which explains when the frquency is above
500 MHZ we should take package length into account.I decided to start designing a zinq based design with ddr3
memory however Xilinx doesn't provide package length info but Altera company does it.please take a look at image I've attached to post,this is so obvious distance from silicon die to chip's pad.my question is do we have to
take them into account?is it possible to do matching length?(lengths differences are noticeable).how can I get Xilinx info based length like Altera's one?
I'm wondering if anyone could help me.
Recently I came across the topic package length in some articles which explains when the frquency is above
500 MHZ we should take package length into account.I decided to start designing a zinq based design with ddr3
memory however Xilinx doesn't provide package length info but Altera company does it.please take a look at image I've attached to post,this is so obvious distance from silicon die to chip's pad.my question is do we have to
take them into account?is it possible to do matching length?(lengths differences are noticeable).how can I get Xilinx info based length like Altera's one?
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