Hello,
​When design DDR3 I intend to add test pad/ via to see eye diagram of DDR3 signal, but I know that add via mean introduce some mismatch and make SI worse. Lacking of via I will don't know what happen in DDRx signals. The consideration should be choose size of pad/via to minimize the affect? Is there any good solution?
​When design DDR3 I intend to add test pad/ via to see eye diagram of DDR3 signal, but I know that add via mean introduce some mismatch and make SI worse. Lacking of via I will don't know what happen in DDRx signals. The consideration should be choose size of pad/via to minimize the affect? Is there any good solution?
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