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Custom board design based on iMX7D

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  • Custom board design based on iMX7D

    Hi,
    I want to design a board for iMX7D (MCIMX7D7DVM10SD) processor. I want to use total 2GB Mobile LPDDR3 SDRAM. I want to use LPDDR3 from Micron (MT52L256M32D1PF or MT52L512M32D2PF or MT52L1G32D4PG).
    There are 3 different configurations for DRAM (1 Gig x 32, 512 Meg x 32, 256 Meg x 32) and I didn't understand well.
    Does the configuration 512 Meg x 32 mean that 2GB of total memory on one chip with 2 die? Can I use this chip and have 2GigaByte of memory?

    I also don't understand how I connect memory chip and processor:

    The memory chip has no BA (Bank Addres), CAS (Column Address Strobe), RAS (Row Address Strobe), WE (write enable), RESET balls. Shall I leave those balls of processors just floating?
    The memory chip has only 10 address lines. Would other balls (DRAM_ADDR11 to DRAM_ADDR15) of processor be floating?
    The memory chip has only one ODT input. The processor has two ODTs. Shall I connect only ODT0 of processor to chip?

    Thanks.

    Last edited by kahlenberg; 03-21-2019, 07:18 AM.

  • #2
    Depending on your appliacation bandiwdth requirement and if the processor is happy, you might be able to get away with a single channel (1 chip). The most common configuration is using 2 chips though, since this gives you twice the bandwith.

    Connect whichever signals you need and leave the rest floating.

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    • #3
      Thanks for answer.
      The processor MCIMX7D7DVM10SD has 32 bit of DRAM_DATA signals. It means I can not increase bandwidth more thane 32 bit.

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      • #4
        Can you attach screenshots from the datasheet? The datasheets are locked - at least show the first page and the package with pins.

        The memory chip has no BA (Bank Addres), CAS (Column Address Strobe), RAS (Row Address Strobe), WE (write enable), RESET balls. Shall I leave those balls of processors just floating?
        Usually memory chips follow some standard - the footprint is same / compatible between memory chips. It looks to me unusual that chips would not have these signals - but I have not seen iMX7 reference design.

        3 different configurations for DRAM (1 Gig x 32, 512 Meg x 32, 256 Meg x 32)"
        - these are not configuration, these are just different memory sizes ... x 32 is usually size of data bus.

        Does the configuration 512 Meg x 32 mean that 2GB of total memory on one chip with 2 die
        - for 2 die chips you will find two chip selects in the pins

        PS: If you are not sure about memory interface, I highly recommend you to use same memory connection as they have it on reference board.

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